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Towards a Runtime Reconfigurable Network-on-Chip-Based Network Processor
Jürgen Foag, Roman Koch
Institute of Computer Engineering
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Computer Science
Networks on Chips
100%
Reconfigurable Network
100%
Network Processor
100%
Paradigm Shift
50%
High Throughput
50%
Coprocessor
50%
Driven Approach
50%
Intensive Task
50%
Processor Architecture
50%
Wide Area Network
50%