Towards a Runtime Reconfigurable Network-on-Chip-Based Network Processor

The demand for increasing bandwidth in wide-area networks requires for network devices that offer high throughput rates and low latencies. While current network node equipment is solely focused on a pure throughput-driven approach, future concepts have additionally to consider autonomic communication aspects in terms of self-aware networking and service-aware networking. In order to design such a node device, this paper is focused on the conception of an innovative network processor architecture that copes with the mentioned challenges and emphasizes the capabilities which have to be available. As a first step towards this goal, a reconfigurable network coprocessor is realized as a network-on-chip which fulfills computation-intensive task. First implementation results indicate the quantitative benefit of the device with respect to the constraints given by the paradigm shift towards autonomic communication and autonomic computation.