RTeasy - An Algorithmic Design Environment on Register Transfer Level

Hagen Schendel; Carsten Albrecht; Erik Maehle

doi:10.1145/1275571.1275581

RTeasy - An Algorithmic Design Environment on Register Transfer Level

Hagen Schendel, Carsten Albrecht, Erik Maehle

Institute of Computer Engineering

Institute of Computer Engineering

Abstract

Current developer tools and HDLs for system design are powerful instruments and support a variety of abstraction levels but they are too complex for didactic purposes. This paper describes the RTeasy IDE, an algorithmic design environment on register transfer level that has been developed to provide a simple system-design tool for didactic purposes to be used e.g. in introductory courses in computer engineering and digital design. The RTeasy tool suite includes an HDL, a simulator and further design features. As an example, it is applied to the design flow of a shift-multiplier.

Original language	English
DOIs	https://doi.org/10.1145/1275571.1275581
Publication status	Published - 01.12.2004
Event	2004 Workshop on Computer Architecture Education - Held in Conjunction with the 31st International Symposium on Computer Architecture - Munich, Germany Duration: 19.06.2004 → 19.06.2004 Conference number: 102980

Conference

Conference	2004 Workshop on Computer Architecture Education - Held in Conjunction with the 31st International Symposium on Computer Architecture
Abbreviated title	WCAE 2004 and ISCA 2004
Country/Territory	Germany
City	Munich
Period	19.06.04 → 19.06.04

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10.1145/1275571.1275581

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abstract = "Current developer tools and HDLs for system design are powerful instruments and support a variety of abstraction levels but they are too complex for didactic purposes. This paper describes the RTeasy IDE, an algorithmic design environment on register transfer level that has been developed to provide a simple system-design tool for didactic purposes to be used e.g. in introductory courses in computer engineering and digital design. The RTeasy tool suite includes an HDL, a simulator and further design features. As an example, it is applied to the design flow of a shift-multiplier.",

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RTeasy - An Algorithmic Design Environment on Register Transfer Level. / Schendel, Hagen; Albrecht, Carsten; Maehle, Erik.
2004. Paper presented at 2004 Workshop on Computer Architecture Education - Held in Conjunction with the 31st International Symposium on Computer Architecture, Munich, Bavaria, Germany.

Research output: Contribution to conference › Conference Papers › peer-review

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T1 - RTeasy - An Algorithmic Design Environment on Register Transfer Level

AU - Schendel, Hagen

AU - Albrecht, Carsten

AU - Maehle, Erik

N1 - Conference code: 102980

PY - 2004/12/1

Y1 - 2004/12/1

N2 - Current developer tools and HDLs for system design are powerful instruments and support a variety of abstraction levels but they are too complex for didactic purposes. This paper describes the RTeasy IDE, an algorithmic design environment on register transfer level that has been developed to provide a simple system-design tool for didactic purposes to be used e.g. in introductory courses in computer engineering and digital design. The RTeasy tool suite includes an HDL, a simulator and further design features. As an example, it is applied to the design flow of a shift-multiplier.

AB - Current developer tools and HDLs for system design are powerful instruments and support a variety of abstraction levels but they are too complex for didactic purposes. This paper describes the RTeasy IDE, an algorithmic design environment on register transfer level that has been developed to provide a simple system-design tool for didactic purposes to be used e.g. in introductory courses in computer engineering and digital design. The RTeasy tool suite includes an HDL, a simulator and further design features. As an example, it is applied to the design flow of a shift-multiplier.

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U2 - 10.1145/1275571.1275581

DO - 10.1145/1275571.1275581

M3 - Conference Papers

T2 - 2004 Workshop on Computer Architecture Education - Held in Conjunction with the 31st International Symposium on Computer Architecture

Y2 - 19 June 2004 through 19 June 2004

ER -

RTeasy - An Algorithmic Design Environment on Register Transfer Level

Abstract

Conference

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