Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits

Francesco Regazzoni; Thomas Eisenbarth; Johann Grossschadl; Luca Breveglieri; Paolo Ienne; Israel Koren; Christof Paar

doi:10.1109/DFT.2007.61

Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits

Francesco Regazzoni, Thomas Eisenbarth, Johann Grossschadl, Luca Breveglieri, Paolo Ienne, Israel Koren, Christof Paar

Institute of IT-Security

Abstract

Many side-channel attacks on implementations of cryptographic algorithms have been developed in recent years demonstrating the ease of extracting the secret key. In response, various schemes to protect cryptographic devices against such attacks have been devised and some implemented in practice. Almost all of these protection schemes target an individual side-channel attack and consequently, it is not obvious whether a scheme for protecting the device against one type of side- channel attacks may make the device more vulnerable to another type of side-channel attacks. We examine in this paper the possibility of such a negative impact for the case where fault detection circuitry is added to a device (to protect it against fault injection attacks) and analyze the resistance of the modified device to power attacks. To simplify the analysis we focus on only one component in the cryptographic device (namely, the S-box in the AES and Kasumi ciphers), and perform power attacks on the original implementation and on a modified implementation with an added parity check circuit. Our results show that the presence of the parity check circuitry has a negative impact on the resistance of the device to power analysis attacks.

Original language	English
Title of host publication	22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy.
Number of pages	9
Publisher	IEEE
Publication date	22.10.2007
Pages	508-516
ISBN (Print)	978-0-7695-2885-6
ISBN (Electronic)	978-0-7695-2885-4
DOIs	https://doi.org/10.1109/DFT.2007.61
Publication status	Published - 22.10.2007
Event	22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) - Rome, Italy Duration: 26.09.2007 → 28.09.2007

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Regazzoni, F., Eisenbarth, T., Grossschadl, J., Breveglieri, L., Ienne, P., Koren, I., & Paar, C. (2007). Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits. In 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy. (pp. 508-516). (International Symposium on Defect and Fault-Tolerance in VLSI Systems). IEEE. https://doi.org/10.1109/DFT.2007.61

Regazzoni, Francesco ; Eisenbarth, Thomas ; Grossschadl, Johann et al. / Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits. 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy.. IEEE, 2007. pp. 508-516 (International Symposium on Defect and Fault-Tolerance in VLSI Systems).

@inproceedings{84cf10e5887345099ec292ed0794fecd,

title = "Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits",

abstract = "Many side-channel attacks on implementations of cryptographic algorithms have been developed in recent years demonstrating the ease of extracting the secret key. In response, various schemes to protect cryptographic devices against such attacks have been devised and some implemented in practice. Almost all of these protection schemes target an individual side-channel attack and consequently, it is not obvious whether a scheme for protecting the device against one type of side- channel attacks may make the device more vulnerable to another type of side-channel attacks. We examine in this paper the possibility of such a negative impact for the case where fault detection circuitry is added to a device (to protect it against fault injection attacks) and analyze the resistance of the modified device to power attacks. To simplify the analysis we focus on only one component in the cryptographic device (namely, the S-box in the AES and Kasumi ciphers), and perform power attacks on the original implementation and on a modified implementation with an added parity check circuit. Our results show that the presence of the parity check circuitry has a negative impact on the resistance of the device to power analysis attacks.",

author = "Francesco Regazzoni and Thomas Eisenbarth and Johann Grossschadl and Luca Breveglieri and Paolo Ienne and Israel Koren and Christof Paar",

year = "2007",

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Regazzoni, F, Eisenbarth, T, Grossschadl, J, Breveglieri, L, Ienne, P, Koren, I & Paar, C 2007, Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits. in 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy.. International Symposium on Defect and Fault-Tolerance in VLSI Systems, IEEE, pp. 508-516, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), Rome, Italy, 26.09.07. https://doi.org/10.1109/DFT.2007.61

Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits. / Regazzoni, Francesco; Eisenbarth, Thomas; Grossschadl, Johann et al.
22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy.. IEEE, 2007. p. 508-516 (International Symposium on Defect and Fault-Tolerance in VLSI Systems).

Research output: Chapters in Books/Reports/Conference Proceedings › Conference contribution › peer-review

TY - GEN

T1 - Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits

AU - Regazzoni, Francesco

AU - Eisenbarth, Thomas

AU - Grossschadl, Johann

AU - Breveglieri, Luca

AU - Ienne, Paolo

AU - Koren, Israel

AU - Paar, Christof

PY - 2007/10/22

Y1 - 2007/10/22

N2 - Many side-channel attacks on implementations of cryptographic algorithms have been developed in recent years demonstrating the ease of extracting the secret key. In response, various schemes to protect cryptographic devices against such attacks have been devised and some implemented in practice. Almost all of these protection schemes target an individual side-channel attack and consequently, it is not obvious whether a scheme for protecting the device against one type of side- channel attacks may make the device more vulnerable to another type of side-channel attacks. We examine in this paper the possibility of such a negative impact for the case where fault detection circuitry is added to a device (to protect it against fault injection attacks) and analyze the resistance of the modified device to power attacks. To simplify the analysis we focus on only one component in the cryptographic device (namely, the S-box in the AES and Kasumi ciphers), and perform power attacks on the original implementation and on a modified implementation with an added parity check circuit. Our results show that the presence of the parity check circuitry has a negative impact on the resistance of the device to power analysis attacks.

AB - Many side-channel attacks on implementations of cryptographic algorithms have been developed in recent years demonstrating the ease of extracting the secret key. In response, various schemes to protect cryptographic devices against such attacks have been devised and some implemented in practice. Almost all of these protection schemes target an individual side-channel attack and consequently, it is not obvious whether a scheme for protecting the device against one type of side- channel attacks may make the device more vulnerable to another type of side-channel attacks. We examine in this paper the possibility of such a negative impact for the case where fault detection circuitry is added to a device (to protect it against fault injection attacks) and analyze the resistance of the modified device to power attacks. To simplify the analysis we focus on only one component in the cryptographic device (namely, the S-box in the AES and Kasumi ciphers), and perform power attacks on the original implementation and on a modified implementation with an added parity check circuit. Our results show that the presence of the parity check circuitry has a negative impact on the resistance of the device to power analysis attacks.

UR - https://www.semanticscholar.org/paper/Power-Attacks-Resistance-of-Cryptographic-S-boxes-Regazzoni-Eisenbarth/1133cd73209bc32351fcdcf904bd25085f342c86

U2 - 10.1109/DFT.2007.61

DO - 10.1109/DFT.2007.61

M3 - Conference contribution

SN - 978-0-7695-2885-6

T3 - International Symposium on Defect and Fault-Tolerance in VLSI Systems

SP - 508

EP - 516

BT - 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy.

PB - IEEE

T2 - 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)

Y2 - 26 September 2007 through 28 September 2007

ER -

Regazzoni F, Eisenbarth T, Grossschadl J, Breveglieri L, Ienne P, Koren I et al. Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits. In 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy.. IEEE. 2007. p. 508-516. (International Symposium on Defect and Fault-Tolerance in VLSI Systems). doi: 10.1109/DFT.2007.61

Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits

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