Power analysis of the t-private logic style for FPGAs

Zachary N.  Goddard; Nicholas  LaJeunesse; Thomas Eisenbarth

doi:10.1109/HST.2015.7140239

Power analysis of the t-private logic style for FPGAs

Zachary N. Goddard, Nicholas LaJeunesse, Thomas Eisenbarth

Institute of IT-Security

Worcester Polytechnic Institute

Abstract

The goal of t-private circuits is to protect information processed by the circuit. This work presents the first practical power analysis evaluation of t-private logic style for FPGAs. Following the synthesis technique introduced at HOST 2012, a t-private S-box of the Present block cipher is synthesized and analyzed with respect to side channel leakage. The analysis is performed on simulated power traces as well as real power measurements taken from an implementation on a Virtex 5 FPGA. Classical Correlation power analysis and Correlation enhanced collision analysis are applied to detect first order leakages. Our results reveal a remaining first-order side channel attack vulnerability.

Original language	English
Title of host publication	2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)
Number of pages	4
Publisher	IEEE
Publication date	02.07.2015
Pages	68-71
ISBN (Electronic)	978-1-4673-7421-7
DOIs	https://doi.org/10.1109/HST.2015.7140239
Publication status	Published - 02.07.2015
Event	2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) - Washington, United States Duration: 05.05.2015 → 07.05.2015

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@inproceedings{12273141e1974cd69a9808766acf8989,

title = "Power analysis of the t-private logic style for FPGAs",

abstract = "The goal of t-private circuits is to protect information processed by the circuit. This work presents the first practical power analysis evaluation of t-private logic style for FPGAs. Following the synthesis technique introduced at HOST 2012, a t-private S-box of the Present block cipher is synthesized and analyzed with respect to side channel leakage. The analysis is performed on simulated power traces as well as real power measurements taken from an implementation on a Virtex 5 FPGA. Classical Correlation power analysis and Correlation enhanced collision analysis are applied to detect first order leakages. Our results reveal a remaining first-order side channel attack vulnerability.",

author = "Goddard, {Zachary N.} and Nicholas LaJeunesse and Thomas Eisenbarth",

year = "2015",

month = jul,

day = "2",

doi = "10.1109/HST.2015.7140239",

language = "English",

series = "Authorized distributor of all IEEE proceedings",

publisher = "IEEE",

pages = "68--71",

booktitle = "2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)",

note = "2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) ; Conference date: 05-05-2015 Through 07-05-2015",

}

Goddard, ZN, LaJeunesse, N & Eisenbarth, T 2015, Power analysis of the t-private logic style for FPGAs. in 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST). Authorized distributor of all IEEE proceedings, IEEE, pp. 68-71, 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Washington, Washington, United States, 05.05.15. https://doi.org/10.1109/HST.2015.7140239

Power analysis of the t-private logic style for FPGAs. / Goddard, Zachary N. ; LaJeunesse, Nicholas ; Eisenbarth, Thomas.
2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST). IEEE, 2015. p. 68-71 (Authorized distributor of all IEEE proceedings).

Research output: Chapters in Books/Reports/Conference Proceedings › Conference contribution › peer-review

TY - GEN

T1 - Power analysis of the t-private logic style for FPGAs

AU - Goddard, Zachary N.

AU - LaJeunesse, Nicholas

AU - Eisenbarth, Thomas

PY - 2015/7/2

Y1 - 2015/7/2

N2 - The goal of t-private circuits is to protect information processed by the circuit. This work presents the first practical power analysis evaluation of t-private logic style for FPGAs. Following the synthesis technique introduced at HOST 2012, a t-private S-box of the Present block cipher is synthesized and analyzed with respect to side channel leakage. The analysis is performed on simulated power traces as well as real power measurements taken from an implementation on a Virtex 5 FPGA. Classical Correlation power analysis and Correlation enhanced collision analysis are applied to detect first order leakages. Our results reveal a remaining first-order side channel attack vulnerability.

AB - The goal of t-private circuits is to protect information processed by the circuit. This work presents the first practical power analysis evaluation of t-private logic style for FPGAs. Following the synthesis technique introduced at HOST 2012, a t-private S-box of the Present block cipher is synthesized and analyzed with respect to side channel leakage. The analysis is performed on simulated power traces as well as real power measurements taken from an implementation on a Virtex 5 FPGA. Classical Correlation power analysis and Correlation enhanced collision analysis are applied to detect first order leakages. Our results reveal a remaining first-order side channel attack vulnerability.

UR - https://www.researchgate.net/publication/283825191_Power_analysis_of_the_t-private_logic_style_for_FPGAS

U2 - 10.1109/HST.2015.7140239

DO - 10.1109/HST.2015.7140239

M3 - Conference contribution

T3 - Authorized distributor of all IEEE proceedings

SP - 68

EP - 71

BT - 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)

PB - IEEE

T2 - 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)

Y2 - 5 May 2015 through 7 May 2015

ER -

Power analysis of the t-private logic style for FPGAs

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