Modelling Tile-Based Run-Time Reconfigurable Systems Using SystemC

In the area of hardware design, there is a noticeable trend towards the use of run-time reconfigurable elements as parts of System-on-Chips (SoCs), SoCs themselves are frequently targeted to reconfigurable platforms such as field programmable gate arrays. This development is a challenge to established high-level modelling and simulation methods which assume a static structure of the simulated system. The present paper describes the extension of the SystemC framework with support for the simulation of run-time reconfiguration of tile-based architectures. The proposed solution is set out in detail and its application to an exemplary reconfigurable SoC design is described.