Latency Reduction of Selected Data Streams in Network-on-Chips for Adaptive Manycore Systems

Thilo Pionteck, Christoph Osterloh, Carsten Albrecht

Abstract

This paper reviews Network-on-Chip architectures with prioritization of selected data streams targeting runtime reconfigurable manycore systems. The common idea of these architectures is to minimize the latency of selected packet transmissions by either bypassing or parallelizing processing stages in routers or by using dedicated links bypassing complete routers. Potential classes of selected data streams are latency critical messages, i.e. cache accesses in multiprocessor systems, or systems with semi-static data streams, i.e. systems in which the same components continuously exchange data for a longer period. The review categorizes the diverse architectures and evaluates their pros and cons in terms of universality, hardware efficiency and support of changing traffic patterns.

Original languageEnglish
Title of host publicationNORCHIP 2010
Number of pages6
PublisherIEEE
Publication date01.12.2010
Pages1-6
Article number5669432
ISBN (Print)978-1-4244-8972-5
ISBN (Electronic)978-1-4244-8973-2, 978-1-4244-8971-8
DOIs
Publication statusPublished - 01.12.2010
Event28th Norchip Conference - Tampere, Finland
Duration: 15.11.201016.11.2010
Conference number: 83479

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