HDL FSM Code Generation Using a MIPS-based Assembler

Dominik Meyer, Marcel Eckert, Bernd Klauer, Jan Haase


The implementation of Finite State Machines (FSMs) is a recurring task in the development of embedded systems when Field Programmable Gate Arrays (FPGAs) or Application Specific Integrated Circuits (ASICs) are being designed. The standard implementation language for these FSMs in this context is a Hardware Description Language (HDL) like VHDL or Verilog. The implementation complexity can rise quickly depending on FSM size and which devices/components are controlled. In many cases FSMs enforce sequential execution of instructions in the concurrent world of FPGAs or ASICs.This paper proposes the use of a MIPS-based assembly dialect and assembler called aFSM to decrease the implementation complexity of such FSMs by automatically generating the FSMs VHDL code. A human VHDL implementation of an Ethernet controller with an FPGA is compared against the implementation with aFSM to evaluate the assembler.

Original languageEnglish
Title of host publication2019 IEEE 28th International Symposium on Industrial Electronics (ISIE)
Number of pages6
Publication date06.2019
Article number8781095
ISBN (Print)978-1-7281-3667-7, 978-1-7281-3665-3
ISBN (Electronic)978-1-7281-3666-0
Publication statusPublished - 06.2019
Event28th IEEE International Symposium on Industrial Electronics - Pinnacle Hotel Harbourfront, Vancouver, Canada
Duration: 12.06.201914.06.2019
Conference number: 150230


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