Hardware-based runtime verification with embedded tracing units and stream processing

Lukas Convent; Sebastian Hungerecker; Torben Scheffel; Malte Schmitz; Daniel Thoma; Alexander Weiss

doi:10.1007/978-3-030-03769-7_5

Hardware-based runtime verification with embedded tracing units and stream processing

Lukas Convent^*, Sebastian Hungerecker, Torben Scheffel, Malte Schmitz, Daniel Thoma, Alexander Weiss

^*Corresponding author for this work

Institute of Software Engineering and Programming Languages

Accemic Technologies GmbH

Abstract

. In this tutorial, we present a comprehensive approach to non-intrusive monitoring of multi-core processors. Modern multi-core processors come with trace-ports that provide a highly compressed trace of the instructions executed by the processor. We describe how these compressed traces can be used to reconstruct the actual control flow trace executed by the program running on the processor and to carry out analyses on the control flow trace in real time using FPGAs. We further give an introduction to the temporal stream-based specification language TeSSLa and show how it can be used to specify typical constraints of a cyber-physical system from the railway domain. Finally, we describe how light-weight, hardware-supported instrumentation can be used to enrich the control-flow trace with data values from the application.

Original language	English
Title of host publication	RV 2018: Runtime Verification
Editors	Christian Colombo, Martin Leucker
Number of pages	21
Volume	11237
Publisher	Springer, Cham
Publication date	08.11.2019
Pages	43-63
ISBN (Print)	978-3-030-03768-0
ISBN (Electronic)	978-3-030-03769-7
DOIs	https://doi.org/10.1007/978-3-030-03769-7_5
Publication status	Published - 08.11.2019
Event	18th International Conference on Runtime Verification - Limassol, Cyprus Duration: 10.11.2018 → 13.11.2018 Conference number: 227239

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Cite this

Convent, L., Hungerecker, S., Scheffel, T., Schmitz, M., Thoma, D., & Weiss, A. (2019). Hardware-based runtime verification with embedded tracing units and stream processing. In C. Colombo, & M. Leucker (Eds.), RV 2018: Runtime Verification (Vol. 11237, pp. 43-63). (Lecture Notes in Computer Science; Vol. 11237). Springer, Cham. https://doi.org/10.1007/978-3-030-03769-7_5

@inproceedings{e83dfd93401b4f0cab12aba7b1326100,

title = "Hardware-based runtime verification with embedded tracing units and stream processing",

abstract = ". In this tutorial, we present a comprehensive approach to non-intrusive monitoring of multi-core processors. Modern multi-core processors come with trace-ports that provide a highly compressed trace of the instructions executed by the processor. We describe how these compressed traces can be used to reconstruct the actual control flow trace executed by the program running on the processor and to carry out analyses on the control flow trace in real time using FPGAs. We further give an introduction to the temporal stream-based specification language TeSSLa and show how it can be used to specify typical constraints of a cyber-physical system from the railway domain. Finally, we describe how light-weight, hardware-supported instrumentation can be used to enrich the control-flow trace with data values from the application.",

author = "Lukas Convent and Sebastian Hungerecker and Torben Scheffel and Malte Schmitz and Daniel Thoma and Alexander Weiss",

note = "Funding Information: This work is supported in part by the European COST Action ARVI, the BMBF project ARAMiS II with funding ID 01 IS 16025, and the European Horizon 2020 project COEMS under number 732016. Publisher Copyright: {\textcopyright} Springer Nature Switzerland AG 2018. Copyright: Copyright 2019 Elsevier B.V., All rights reserved.; 18th International Conference on Runtime Verification , RV 2018 ; Conference date: 10-11-2018 Through 13-11-2018",

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Convent, L, Hungerecker, S, Scheffel, T, Schmitz, M, Thoma, D & Weiss, A 2019, Hardware-based runtime verification with embedded tracing units and stream processing. in C Colombo & M Leucker (eds), RV 2018: Runtime Verification. vol. 11237, Lecture Notes in Computer Science, vol. 11237, Springer, Cham, pp. 43-63, 18th International Conference on Runtime Verification , Limassol, Cyprus, 10.11.18. https://doi.org/10.1007/978-3-030-03769-7_5

Hardware-based runtime verification with embedded tracing units and stream processing. / Convent, Lukas; Hungerecker, Sebastian; Scheffel, Torben et al.
RV 2018: Runtime Verification. ed. / Christian Colombo; Martin Leucker. Vol. 11237 Springer, Cham, 2019. p. 43-63 (Lecture Notes in Computer Science; Vol. 11237).

Research output: Chapters in Books/Reports/Conference Proceedings › Conference contribution › peer-review

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AU - Weiss, Alexander

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AB - . In this tutorial, we present a comprehensive approach to non-intrusive monitoring of multi-core processors. Modern multi-core processors come with trace-ports that provide a highly compressed trace of the instructions executed by the processor. We describe how these compressed traces can be used to reconstruct the actual control flow trace executed by the program running on the processor and to carry out analyses on the control flow trace in real time using FPGAs. We further give an introduction to the temporal stream-based specification language TeSSLa and show how it can be used to specify typical constraints of a cyber-physical system from the railway domain. Finally, we describe how light-weight, hardware-supported instrumentation can be used to enrich the control-flow trace with data values from the application.

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Hardware-based runtime verification with embedded tracing units and stream processing

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