Hardware-based runtime verification with embedded tracing units and stream processing

Lukas Convent*, Sebastian Hungerecker, Torben Scheffel, Malte Schmitz, Daniel Thoma, Alexander Weiss

*Corresponding author for this work


. In this tutorial, we present a comprehensive approach to non-intrusive monitoring of multi-core processors. Modern multi-core processors come with trace-ports that provide a highly compressed trace of the instructions executed by the processor. We describe how these compressed traces can be used to reconstruct the actual control flow trace executed by the program running on the processor and to carry out analyses on the control flow trace in real time using FPGAs. We further give an introduction to the temporal stream-based specification language TeSSLa and show how it can be used to specify typical constraints of a cyber-physical system from the railway domain. Finally, we describe how light-weight, hardware-supported instrumentation can be used to enrich the control-flow trace with data values from the application.

Original languageEnglish
Title of host publicationRV 2018: Runtime Verification
EditorsChristian Colombo, Martin Leucker
Number of pages21
PublisherSpringer, Cham
Publication date08.11.2019
ISBN (Print)978-3-030-03768-0
ISBN (Electronic)978-3-030-03769-7
Publication statusPublished - 08.11.2019
Event18th International Conference on Runtime Verification - Limassol, Cyprus
Duration: 10.11.201813.11.2018
Conference number: 227239


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