Hardware-Accelerated Index Construction for Semantic Web

Christopher Blochwitz; Julian Wolff; Mladen Berekovic; Dennis Heinrich; Sven Groppe; Jan Moritz Joseph; Thilo Pionteck

doi:10.1109/FPT.2018.00053

Hardware-Accelerated Index Construction for Semantic Web

Christopher Blochwitz^*, Julian Wolff, Mladen Berekovic, Dennis Heinrich, Sven Groppe, Jan Moritz Joseph, Thilo Pionteck

^*Corresponding author for this work

Abstract

In this paper, an optimized data structure for managing triples used in a Semantic Web Database and a hardwareengine for index construction are presented. We propose anFPGA-centric design, which we call Hardware-Triplestore. Aspart of the design, a scalable and parallel architecture forTriplestore construction is introduced. We propose a hybrid datastructure consisting of three layers, one for every element ofthe semantic triple. The data structure is optimized for ourhardware-centric design and is stored on an external DDR4-Memory. The Hardware-Triplestore is evaluated separately fromthe rest of the database system and achieves an insertion rateof 1.24 million triples per second, which is 17 times faster thanone of the fastest software Triplestore-RDF-3X-.

Original language	English
Title of host publication	2018 International Conference on Field-Programmable Technology (FPT)
Number of pages	4
Publisher	IEEE
Publication date	12.2018
Pages	281-284
Article number	8742268
ISBN (Print)	978-1-7281-0215-3
ISBN (Electronic)	978-1-7281-0214-6
DOIs	https://doi.org/10.1109/FPT.2018.00053
Publication status	Published - 12.2018
Event	17th International Conference on Field-Programmable Technology - Naha, Japan Duration: 10.12.2018 → 14.12.2018 Conference number: 148864

Research Areas and Centers

Research Area: Intelligent Systems
Centers: Center for Artificial Intelligence Luebeck (ZKIL)

DFG Research Classification Scheme

409-04 Operating, Communication, Database and Distributed Systems

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/FPT.2018.00053

Cite this

@inproceedings{9367a3be1bbc4b1f918d487906118cae,

title = "Hardware-Accelerated Index Construction for Semantic Web",

abstract = "In this paper, an optimized data structure for managing triples used in a Semantic Web Database and a hardwareengine for index construction are presented. We propose anFPGA-centric design, which we call Hardware-Triplestore. Aspart of the design, a scalable and parallel architecture forTriplestore construction is introduced. We propose a hybrid datastructure consisting of three layers, one for every element ofthe semantic triple. The data structure is optimized for ourhardware-centric design and is stored on an external DDR4-Memory. The Hardware-Triplestore is evaluated separately fromthe rest of the database system and achieves an insertion rateof 1.24 million triples per second, which is 17 times faster thanone of the fastest software Triplestore-RDF-3X-.",

author = "Christopher Blochwitz and Julian Wolff and Mladen Berekovic and Dennis Heinrich and Sven Groppe and Joseph, {Jan Moritz} and Thilo Pionteck",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE. Copyright: Copyright 2020 Elsevier B.V., All rights reserved.; 17th International Conference on Field-Programmable Technology , FPT 2018 ; Conference date: 10-12-2018 Through 14-12-2018",

year = "2018",

month = dec,

doi = "10.1109/FPT.2018.00053",

language = "English",

isbn = "978-1-7281-0215-3",

pages = "281--284",

booktitle = "2018 International Conference on Field-Programmable Technology (FPT)",

publisher = "IEEE",

}

Blochwitz, C, Wolff, J, Berekovic, M, Heinrich, D, Groppe, S, Joseph, JM & Pionteck, T 2018, Hardware-Accelerated Index Construction for Semantic Web. in 2018 International Conference on Field-Programmable Technology (FPT)., 8742268, IEEE, pp. 281-284, 17th International Conference on Field-Programmable Technology , Naha, Japan, 10.12.18. https://doi.org/10.1109/FPT.2018.00053

TY - GEN

T1 - Hardware-Accelerated Index Construction for Semantic Web

AU - Blochwitz, Christopher

AU - Wolff, Julian

AU - Berekovic, Mladen

AU - Heinrich, Dennis

AU - Groppe, Sven

AU - Joseph, Jan Moritz

AU - Pionteck, Thilo

N1 - Conference code: 148864

PY - 2018/12

Y1 - 2018/12

N2 - In this paper, an optimized data structure for managing triples used in a Semantic Web Database and a hardwareengine for index construction are presented. We propose anFPGA-centric design, which we call Hardware-Triplestore. Aspart of the design, a scalable and parallel architecture forTriplestore construction is introduced. We propose a hybrid datastructure consisting of three layers, one for every element ofthe semantic triple. The data structure is optimized for ourhardware-centric design and is stored on an external DDR4-Memory. The Hardware-Triplestore is evaluated separately fromthe rest of the database system and achieves an insertion rateof 1.24 million triples per second, which is 17 times faster thanone of the fastest software Triplestore-RDF-3X-.

AB - In this paper, an optimized data structure for managing triples used in a Semantic Web Database and a hardwareengine for index construction are presented. We propose anFPGA-centric design, which we call Hardware-Triplestore. Aspart of the design, a scalable and parallel architecture forTriplestore construction is introduced. We propose a hybrid datastructure consisting of three layers, one for every element ofthe semantic triple. The data structure is optimized for ourhardware-centric design and is stored on an external DDR4-Memory. The Hardware-Triplestore is evaluated separately fromthe rest of the database system and achieves an insertion rateof 1.24 million triples per second, which is 17 times faster thanone of the fastest software Triplestore-RDF-3X-.

UR - https://www.scopus.com/record/display.uri?eid=2-s2.0-85068319866&origin=inward&txGid=6b073d1b83709a266f6311d01bb63b7c

U2 - 10.1109/FPT.2018.00053

DO - 10.1109/FPT.2018.00053

M3 - Conference contribution

SN - 978-1-7281-0215-3

SP - 281

EP - 284

BT - 2018 International Conference on Field-Programmable Technology (FPT)

PB - IEEE

T2 - 17th International Conference on Field-Programmable Technology

Y2 - 10 December 2018 through 14 December 2018

ER -

Hardware-Accelerated Index Construction for Semantic Web

Abstract

Research Areas and Centers

DFG Research Classification Scheme

UN SDGs

Access to Document

Other files and links

Fingerprint

Cite this