Hardware-Accelerated Index Construction for Semantic Web

Christopher Blochwitz*, Julian Wolff, Mladen Berekovic, Dennis Heinrich, Sven Groppe, Jan Moritz Joseph, Thilo Pionteck

*Corresponding author for this work


In this paper, an optimized data structure for managing triples used in a Semantic Web Database and a hardwareengine for index construction are presented. We propose anFPGA-centric design, which we call Hardware-Triplestore. Aspart of the design, a scalable and parallel architecture forTriplestore construction is introduced. We propose a hybrid datastructure consisting of three layers, one for every element ofthe semantic triple. The data structure is optimized for ourhardware-centric design and is stored on an external DDR4-Memory. The Hardware-Triplestore is evaluated separately fromthe rest of the database system and achieves an insertion rateof 1.24 million triples per second, which is 17 times faster thanone of the fastest software Triplestore-RDF-3X-.

Original languageEnglish
Title of host publication2018 International Conference on Field-Programmable Technology (FPT)
Number of pages4
Publication date12.2018
Article number8742268
ISBN (Print)978-1-7281-0215-3
ISBN (Electronic)978-1-7281-0214-6
Publication statusPublished - 12.2018
Event17th International Conference on Field-Programmable Technology - Naha, Japan
Duration: 10.12.201814.12.2018
Conference number: 148864

Research Areas and Centers

  • Research Area: Intelligent Systems
  • Centers: Center for Artificial Intelligence Luebeck (ZKIL)

DFG Research Classification Scheme

  • 409-04 Operating, Communication, Database and Distributed Systems


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