Generating Addresses for Multi-dimensional Array Access in FPGA On-chip Memory

A. C. Döring; G. Lustig

doi:10.1007/3-540-44614-1_67

Generating Addresses for Multi-dimensional Array Access in FPGA On-chip Memory

A. C. Döring, G. Lustig

Abstract

Multidimensional arrays are among the most common data types. Their use in configurable hardware requires the injective translation of the index tuple into a memory address. This problem is considered in the paper, searching for a balance between speed and waste of memory. The basic idea is to divide one of the index ranges such that one part is a power of two. In this way the indices can be concatenated with fewer loss. To combine both resulting parts into one memory, several techniques are used. The integration of the proposed method into libraries and tools allows efficient description of algorithms on a higher abstraction level.

Original language	English
Title of host publication	FPL 2000: Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing
Number of pages	10
Volume	1896
Publisher	Springer Verlag
Publication date	01.01.2000
Pages	626-635
ISBN (Print)	978-3-540-67899-1
ISBN (Electronic)	978-3-540-44614-9
DOIs	https://doi.org/10.1007/3-540-44614-1_67
Publication status	Published - 01.01.2000
Externally published	Yes
Event	10th International Conference on Field-Programmable Logic and Applications - Villach, Austria Duration: 27.08.2000 → 30.08.2000 Conference number: 131899

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10.1007/3-540-44614-1_67

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@inproceedings{0325043bb00b4d0fbca21380fcd1fc15,

title = "Generating Addresses for Multi-dimensional Array Access in FPGA On-chip Memory",

abstract = "Multidimensional arrays are among the most common data types. Their use in configurable hardware requires the injective translation of the index tuple into a memory address. This problem is considered in the paper, searching for a balance between speed and waste of memory. The basic idea is to divide one of the index ranges such that one part is a power of two. In this way the indices can be concatenated with fewer loss. To combine both resulting parts into one memory, several techniques are used. The integration of the proposed method into libraries and tools allows efficient description of algorithms on a higher abstraction level.",

author = "D{\"o}ring, {A. C.} and G. Lustig",

year = "2000",

month = jan,

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doi = "10.1007/3-540-44614-1_67",

language = "English",

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volume = "1896",

series = "Lecture Notes in Computer Science",

publisher = "Springer Verlag",

pages = "626--635",

booktitle = "FPL 2000: Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing",

note = "10th International Conference on Field-Programmable Logic and Applications <br/>, FPL 2000 ; Conference date: 27-08-2000 Through 30-08-2000",

}

Döring, AC & Lustig, G 2000, Generating Addresses for Multi-dimensional Array Access in FPGA On-chip Memory. in FPL 2000: Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing . vol. 1896, Lecture Notes in Computer Science, vol. 1896, Springer Verlag, pp. 626-635, 10th International Conference on Field-Programmable Logic and Applications
, Villach, Austria, 27.08.00. https://doi.org/10.1007/3-540-44614-1_67

Generating Addresses for Multi-dimensional Array Access in FPGA On-chip Memory. / Döring, A. C.; Lustig, G.
FPL 2000: Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing . Vol. 1896 Springer Verlag, 2000. p. 626-635 (Lecture Notes in Computer Science; Vol. 1896).

Research output: Chapters in Books/Reports/Conference Proceedings › Conference contribution › peer-review

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N2 - Multidimensional arrays are among the most common data types. Their use in configurable hardware requires the injective translation of the index tuple into a memory address. This problem is considered in the paper, searching for a balance between speed and waste of memory. The basic idea is to divide one of the index ranges such that one part is a power of two. In this way the indices can be concatenated with fewer loss. To combine both resulting parts into one memory, several techniques are used. The integration of the proposed method into libraries and tools allows efficient description of algorithms on a higher abstraction level.

AB - Multidimensional arrays are among the most common data types. Their use in configurable hardware requires the injective translation of the index tuple into a memory address. This problem is considered in the paper, searching for a balance between speed and waste of memory. The basic idea is to divide one of the index ranges such that one part is a power of two. In this way the indices can be concatenated with fewer loss. To combine both resulting parts into one memory, several techniques are used. The integration of the proposed method into libraries and tools allows efficient description of algorithms on a higher abstraction level.

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DO - 10.1007/3-540-44614-1_67

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BT - FPL 2000: Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing

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T2 - 10th International Conference on Field-Programmable Logic and Applications <br/>

Y2 - 27 August 2000 through 30 August 2000

ER -

Generating Addresses for Multi-dimensional Array Access in FPGA On-chip Memory

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