Experiences with a FPGA-based Reed/Solomon Encoding Coprocessor

Volker Hampel, Peter Sobe, Erik Maehle

Abstract

In this paper we present an implementation of a Reed/Solomon (R/S) coprocessor to be used on a hybrid computing system, which combines general purpose CPUs with FPGAs. The coprocessor accelerates the encoding of user data to be stored block-wise on a distributed, failure tolerant storage system. We document design constraints and their impact on the resulting architecture. Measurements are presented to characterize the performance of the coprocessor in terms of computation bandwidth, latency, and the hardware-software interaction. For comparison, software based R/S encoding implementations are presented and evaluated as well. Finally, the performance of the hardware accelerated encoding is compared to a software based system.

Original languageEnglish
Title of host publication10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)
Number of pages8
PublisherIEEE
Publication date01.12.2007
Pages77-84
Article number4341453
ISBN (Print)978-0-7695-2978-X, 978-0-7695-2978-3
DOIs
Publication statusPublished - 01.12.2007
Event10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
- Lübeck, Germany
Duration: 29.08.200731.08.2007
Conference number: 72733

Fingerprint

Dive into the research topics of 'Experiences with a FPGA-based Reed/Solomon Encoding Coprocessor'. Together they form a unique fingerprint.

Cite this