Abstract
In this paper we present an implementation of a Reed/Solomon (R/S) coprocessor to be used on a hybrid computing system, which combines general purpose CPUs with FPGAs. The coprocessor accelerates the encoding of user data to be stored block-wise on a distributed, failure tolerant storage system. We document design constraints and their impact on the resulting architecture. Measurements are presented to characterize the performance of the coprocessor in terms of computation bandwidth, latency, and the hardware-software interaction. For comparison, software based R/S encoding implementations are presented and evaluated as well. Finally, the performance of the hardware accelerated encoding is compared to a software based system.
Original language | English |
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Title of host publication | 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007) |
Number of pages | 8 |
Publisher | IEEE |
Publication date | 01.12.2007 |
Pages | 77-84 |
Article number | 4341453 |
ISBN (Print) | 978-0-7695-2978-X, 978-0-7695-2978-3 |
DOIs | |
Publication status | Published - 01.12.2007 |
Event | 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools - Lübeck, Germany Duration: 29.08.2007 → 31.08.2007 Conference number: 72733 |