DynaCORE-dynamically reconfigurable coprocessor for network processors

Carsten Albrecht; Jürgen Foag; Roman Koch; Erik Maehle; Thilo Pionteck

doi:10.1007/978-90-481-3485-4_16

DynaCORE-dynamically reconfigurable coprocessor for network processors

Carsten Albrecht, Jürgen Foag, Roman Koch, Erik Maehle, Thilo Pionteck

Institute of Computer Engineering

3 Citations (Scopus)

Abstract

This chapter presents DynaCORE, a dynamically reconfigurable coprocessor architecture for network processors. The architecture takes over computationally intensive tasks from network processors and provides dynamically exchangeable hardware assists for complex payload processing. According to the actual traffic profile, DynaCORE autonomously determines an optimal set of hardware assists. The hardware assists reside in a grid of exchangeable tiles which are connected by a runtime adaptable network-on-chip. System simulation, hardware architecture as well as reconfiguration management strategies are presented within this chapter.

Original language	English
Title of host publication	Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications
Number of pages	20
Publisher	Springer Netherlands
Publication date	01.12.2010
Pages	335-354
ISBN (Print)	978-90-481-3484-7
ISBN (Electronic)	978-90-481-3485-4
DOIs	https://doi.org/10.1007/978-90-481-3485-4_16
Publication status	Published - 01.12.2010

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 9 Industry, Innovation, and Infrastructure

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DynaCORE-dynamically reconfigurable coprocessor for network processors

Abstract

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