Digital Hardware Synthesis as a Cloud Service

Dominik Meyer, Jan Haase, Marcel Eckert, Bernd Klauer


Synthesizing hardware from a Hardware Description Lan- guage (HDL) for Field Programmable Gate Arrays (FPGAs) and Applica- tion Specific Integrated Circuits (ASICs) is very important today because many companies produce ASICs or use FPGAs for prototyping or High Performance Computing (HPC). Although, the synthesis, mapping and routing processes are well understood and well covered by research, some challenges in the operation of these processes exist, such as easy design space exploration, commercial license management, and different software version support which are not fully addressed yet. This paper describes a cloud based service for digital hardware synthesis. Through this service the standard synthesis flow is distributed onto a cluster of dedicated servers or Virtual Machines (VMs) located in the Internet. It easily supports running many synthesis jobs of the same hardware description but with different design flows, concurrently. This feature can be used for easy design space exploration and testing. A cloud based service also reduces the hardware and software requirements for the development system.
Original languageEnglish
Publication statusPublished - 01.09.2016
EventFDL 2016 : Forum on specification & Design Languages - Bremen, Germany
Duration: 14.09.201616.09.2016


ConferenceFDL 2016 : Forum on specification & Design Languages


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