Designing Coprocessors for Hybrid Compute Systems

Volker Hampel; Peter Sobe; Erik Maehle

doi:10.1109/IPDPS.2008.4536506

Designing Coprocessors for Hybrid Compute Systems

Volker Hampel, Peter Sobe, Erik Maehle

Institute of Computer Engineering

1 Citation (Scopus)

Abstract

A Hybrid Compute System (HCS) combines standard CPUs and reconfigurable devices, usually FPGAs, in one system. Recently, these systems have become more attractive again, due to a closer and hence faster coupling of both computational components. From our work with several designs for the same application, we have found the communication between a CPU and a FPGA-based coprocessor to relate either to pipelining or to a bulk-wise transfer with buffered data processing. We identify conditions which determine whether the pipelined or the buffered style should be used in a design. A Reed/Solomon encoding coprocessor has been implemented for each of the communication architectures to serve as an example of how these conditions materialize and how they influence the performance.

Original language	English
Title of host publication	2008 IEEE International Symposium on Parallel and Distributed Processing
Number of pages	8
Publisher	IEEE
Publication date	10.09.2008
Pages	1-8
Article number	4536506
ISBN (Print)	978-1-4244-1693-6 , 978-1-4244-1694-3
DOIs	https://doi.org/10.1109/IPDPS.2008.4536506
Publication status	Published - 10.09.2008
Event	22nd IEEE International Parallel and Distributed Processing Symposium - Miami, United States Duration: 14.04.2008 → 18.04.2008 Conference number: 73339

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10.1109/IPDPS.2008.4536506

Cite this

@inproceedings{d589307fb3dd495197c3542990b66882,

title = "Designing Coprocessors for Hybrid Compute Systems",

abstract = "A Hybrid Compute System (HCS) combines standard CPUs and reconfigurable devices, usually FPGAs, in one system. Recently, these systems have become more attractive again, due to a closer and hence faster coupling of both computational components. From our work with several designs for the same application, we have found the communication between a CPU and a FPGA-based coprocessor to relate either to pipelining or to a bulk-wise transfer with buffered data processing. We identify conditions which determine whether the pipelined or the buffered style should be used in a design. A Reed/Solomon encoding coprocessor has been implemented for each of the communication architectures to serve as an example of how these conditions materialize and how they influence the performance.",

author = "Volker Hampel and Peter Sobe and Erik Maehle",

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isbn = "978-1-4244-1693-6 ",

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publisher = "IEEE",

pages = "1--8",

booktitle = "2008 IEEE International Symposium on Parallel and Distributed Processing",

note = "22nd IEEE International Parallel and Distributed Processing Symposium <br/>, IPDPS 2008 ; Conference date: 14-04-2008 Through 18-04-2008",

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Hampel, V, Sobe, P & Maehle, E 2008, Designing Coprocessors for Hybrid Compute Systems. in 2008 IEEE International Symposium on Parallel and Distributed Processing., 4536506, IEEE International Parallel and Distributed Processing Symposium, Program and CD-ROM, IEEE, pp. 1-8, 22nd IEEE International Parallel and Distributed Processing Symposium
, Miami, Florida, United States, 14.04.08. https://doi.org/10.1109/IPDPS.2008.4536506

Designing Coprocessors for Hybrid Compute Systems. / Hampel, Volker; Sobe, Peter; Maehle, Erik.
2008 IEEE International Symposium on Parallel and Distributed Processing. IEEE, 2008. p. 1-8 4536506 (IEEE International Parallel and Distributed Processing Symposium, Program and CD-ROM).

Research output: Chapters in Books/Reports/Conference Proceedings › Conference contribution › peer-review

TY - GEN

T1 - Designing Coprocessors for Hybrid Compute Systems

AU - Hampel, Volker

AU - Sobe, Peter

AU - Maehle, Erik

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N2 - A Hybrid Compute System (HCS) combines standard CPUs and reconfigurable devices, usually FPGAs, in one system. Recently, these systems have become more attractive again, due to a closer and hence faster coupling of both computational components. From our work with several designs for the same application, we have found the communication between a CPU and a FPGA-based coprocessor to relate either to pipelining or to a bulk-wise transfer with buffered data processing. We identify conditions which determine whether the pipelined or the buffered style should be used in a design. A Reed/Solomon encoding coprocessor has been implemented for each of the communication architectures to serve as an example of how these conditions materialize and how they influence the performance.

AB - A Hybrid Compute System (HCS) combines standard CPUs and reconfigurable devices, usually FPGAs, in one system. Recently, these systems have become more attractive again, due to a closer and hence faster coupling of both computational components. From our work with several designs for the same application, we have found the communication between a CPU and a FPGA-based coprocessor to relate either to pipelining or to a bulk-wise transfer with buffered data processing. We identify conditions which determine whether the pipelined or the buffered style should be used in a design. A Reed/Solomon encoding coprocessor has been implemented for each of the communication architectures to serve as an example of how these conditions materialize and how they influence the performance.

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BT - 2008 IEEE International Symposium on Parallel and Distributed Processing

PB - IEEE

T2 - 22nd IEEE International Parallel and Distributed Processing Symposium <br/>

Y2 - 14 April 2008 through 18 April 2008

ER -

Designing Coprocessors for Hybrid Compute Systems

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