Designing Coprocessors for Hybrid Compute Systems

Volker Hampel, Peter Sobe, Erik Maehle


A Hybrid Compute System (HCS) combines standard CPUs and reconfigurable devices, usually FPGAs, in one system. Recently, these systems have become more attractive again, due to a closer and hence faster coupling of both computational components. From our work with several designs for the same application, we have found the communication between a CPU and a FPGA-based coprocessor to relate either to pipelining or to a bulk-wise transfer with buffered data processing. We identify conditions which determine whether the pipelined or the buffered style should be used in a design. A Reed/Solomon encoding coprocessor has been implemented for each of the communication architectures to serve as an example of how these conditions materialize and how they influence the performance.

Original languageEnglish
Title of host publication 2008 IEEE International Symposium on Parallel and Distributed Processing
Number of pages8
Publication date10.09.2008
Article number4536506
ISBN (Print)978-1-4244-1693-6 , 978-1-4244-1694-3
Publication statusPublished - 10.09.2008
Event22nd IEEE International Parallel and Distributed Processing Symposium
- Miami, United States
Duration: 14.04.200818.04.2008
Conference number: 73339


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