Design and Simulation of Runtime Reconfigurable Systems

This paper presents an architectural framework and simulation model for tile-based runtime reconfigurable systems. The framework accounts for all hardware limitations of actual FPGA devices and is based on the division of the reconfigurable system partition into a set of small tiles. These tiles can either be exchanged individually at runtime or can be grouped to larger tiles and be exchanged as a whole. The adaptive tile size allows the realization of hardware modules of varying sizes. For easing the system design process a SystemC simulation methodology at a high abstraction level is presented which provides support for all architectural features of the hardware framework. In particular, the capability of simulating runtime reconfigurable systems is supported by the simulation methodology without modifying the SystemC kernel. The applicability of the architectural framework and of the simulation model is demonstrated by means of an example.