This work presents a new approach for monitoring and debugging RTL logic on FPGAs-Live-Tracing-Logic. The design combines the two most common approaches for debugging RTL logic, Scan-Chains and Trace-Buffers, while avoiding their disadvantage: First, slow and clock-controlled scans of the Scan-Chains, second, a limited time period for tracing of Trace-Buffers, respectively. The Live-Tracing-Logic connects trace-buffer modules serially, monitors signal events continuously, transmits the collected data to the host system via a high bandwidth PCIe interface, and converts the data into a VCD file. Furthermore, an automatic tool flow is introduced, which requires only two user interactions: First, using pragmas, second, starting a TCL script. The Live-Tracing-Logic is evaluated for different workloads and different tracing modes. The results show that the architecture has the capacity to continuously trace up to 3.10 GB/s of data and is only limited by the PCIe interface. Furthermore, the Live-Tracing-Logic is suitable for multi clock designs and utilizes up to 70 % less resources in comparison to the Integrated Logic Analyzer of Xilinx.
|Title of host publication||2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)|
|Number of pages||8|
|Publication status||Published - 01.12.2017|
|Event||2017 International Conference on Reconfigurable Computing and FPGAs - Cancun, Mexico|
Duration: 04.12.2017 → 06.12.2017