Using caches is a common technique to enhance the computational performance of a processor which would otherwise be limited by the timing of a systems main memory. Softcores instantiated inside an FPGA also require caches to achieve a suitable computational performance whenever they use large amounts of memory provided by FPGA external memory resources like DDR-memory. However, the internal structures of an FPGA limit the freedom in designing caches for theses softcores. Therefore, this paper examines the impact of several cache parameters like the total cache size and the degree of associativity on the resource usage, system clock frequency and resulting computational performance of a softcore base system inside an FPGA. As a result, design guidelines/rules for parameterizing softcore-caches within an FPGA are deduced.
|Title of host publication||2017 International Conference on FPGA Reconfiguration for General-Purpose Computing (FPGA4GPC)|
|Number of pages||6|
|Publication status||Published - 01.05.2017|
|Event||2nd International Conference on FPGA Reconfiguration for General-Purpose Computing - Helmut-Schmidt-University, Hamburg, Germany|
Duration: 09.05.2017 → 10.05.2017