Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs

J. M. Joseph; C. Blochwitz; T. Pionteck; Alberto García-Ortiz

doi:10.1109/NORCHIP.2015.7364370

Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs

J. M. Joseph, C. Blochwitz, T. Pionteck, Alberto García-Ortiz

Institute of Computer Engineering

University of Bremen

Abstract

In this paper, optimizations for asymmetric Network-on-Chip (NoC) router architectures are proposed for heterogeneous 3D-System-on-Chips (SoCs). The optimizations cover buffer reorganization among dies and focus on power and area savings. The architectures are compared to conventional, symmetric routers on the bases of synthesizable RTL models. Area savings of 8.3% and power savings of 5.4% for link buffers are achieved while accepting a minor average system performance loss of 2.1% in simulations. We thereby demonstrate the potentials of asymmetric NoC designs for heterogeneous 3D-SoCs.

Original language	English
Title of host publication	2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP International Symposium on System-on-Chip (SoC)
Number of pages	4
Place of Publication	Oslo, Norway
Publisher	IEEE
Publication date	01.10.2015
Pages	1-4
ISBN (Print)	978-1-4673-6575-8
ISBN (Electronic)	978-1-4673-6576-5
DOIs	https://doi.org/10.1109/NORCHIP.2015.7364370
Publication status	Published - 01.10.2015
Event	1st IEEE Nordic Circuits and Systems Conference - Oslo, Norway Duration: 26.10.2015 → 28.10.2015

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This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/NORCHIP.2015.7364370

Cite this

@inproceedings{73ed6788fe2c496eac5d49d3da18fff7,

title = "Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs",

abstract = "In this paper, optimizations for asymmetric Network-on-Chip (NoC) router architectures are proposed for heterogeneous 3D-System-on-Chips (SoCs). The optimizations cover buffer reorganization among dies and focus on power and area savings. The architectures are compared to conventional, symmetric routers on the bases of synthesizable RTL models. Area savings of 8.3% and power savings of 5.4% for link buffers are achieved while accepting a minor average system performance loss of 2.1% in simulations. We thereby demonstrate the potentials of asymmetric NoC designs for heterogeneous 3D-SoCs.",

author = "Joseph, {J. M.} and C. Blochwitz and T. Pionteck and Alberto Garc{\'i}a-Ortiz",

year = "2015",

month = oct,

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doi = "10.1109/NORCHIP.2015.7364370",

language = "English",

isbn = "978-1-4673-6575-8",

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publisher = "IEEE",

pages = "1--4",

booktitle = "2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP International Symposium on System-on-Chip (SoC)",

note = "1st IEEE Nordic Circuits and Systems Conference, NORCAS 2015 ; Conference date: 26-10-2015 Through 28-10-2015",

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Joseph, JM, Blochwitz, C, Pionteck, T & García-Ortiz, A 2015, Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs. in 2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP International Symposium on System-on-Chip (SoC). IEEE Proceedings, IEEE, Oslo, Norway, pp. 1-4, 1st IEEE Nordic Circuits and Systems Conference, Oslo, Norway, 26.10.15. https://doi.org/10.1109/NORCHIP.2015.7364370

Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs. / Joseph, J. M.; Blochwitz, C.; Pionteck, T. et al.
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP International Symposium on System-on-Chip (SoC). Oslo, Norway: IEEE, 2015. p. 1-4 (IEEE Proceedings).

Research output: Chapters in Books/Reports/Conference Proceedings › Conference contribution › peer-review

TY - GEN

T1 - Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs

AU - Joseph, J. M.

AU - Blochwitz, C.

AU - Pionteck, T.

AU - García-Ortiz, Alberto

PY - 2015/10/1

Y1 - 2015/10/1

N2 - In this paper, optimizations for asymmetric Network-on-Chip (NoC) router architectures are proposed for heterogeneous 3D-System-on-Chips (SoCs). The optimizations cover buffer reorganization among dies and focus on power and area savings. The architectures are compared to conventional, symmetric routers on the bases of synthesizable RTL models. Area savings of 8.3% and power savings of 5.4% for link buffers are achieved while accepting a minor average system performance loss of 2.1% in simulations. We thereby demonstrate the potentials of asymmetric NoC designs for heterogeneous 3D-SoCs.

AB - In this paper, optimizations for asymmetric Network-on-Chip (NoC) router architectures are proposed for heterogeneous 3D-System-on-Chips (SoCs). The optimizations cover buffer reorganization among dies and focus on power and area savings. The architectures are compared to conventional, symmetric routers on the bases of synthesizable RTL models. Area savings of 8.3% and power savings of 5.4% for link buffers are achieved while accepting a minor average system performance loss of 2.1% in simulations. We thereby demonstrate the potentials of asymmetric NoC designs for heterogeneous 3D-SoCs.

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M3 - Conference contribution

SN - 978-1-4673-6575-8

T3 - IEEE Proceedings

SP - 1

EP - 4

BT - 2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP International Symposium on System-on-Chip (SoC)

PB - IEEE

CY - Oslo, Norway

T2 - 1st IEEE Nordic Circuits and Systems Conference

Y2 - 26 October 2015 through 28 October 2015

ER -

Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs

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Detection and adaptive prioritization of semi-static data streams and traffic patterns in Network-on-Chips

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Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs

Abstract

UN SDGs

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Detection and adaptive prioritization of semi-static data streams and traffic patterns in Network-on-Chips

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