This article presents the architecture conception of a reconfigurable network coprocessor platform (Dyna-Core). The system represents an offload engine for computation-intensive tasks and provides both, func-tional flexibility and high-performance processing ca-pability. Here, field-programmable gate arrays are used to overcome throughput limitations of current net-work processor devices (NPs) and systems realized by NPs extended by external task-specific hardware accel-erators, respectively. The exploitation of partial dy-namic reconfiguration allows a rapid adaptation to-wards modified system behaviors. In order to achieve the flexibility, fundamental considerations concerning the efficient architecture design of the system are dis-cussed and results derived from timing simulations are given.
|Title of host publication
|Published - 01.03.2019