Applying Partial Reconfiguration to Networks-on-Chips

Thilo Pionteck, Roman Koch, Carsten Albrecht


This paper presents CoNoChi, an adaptable Network-on-Chip for dynamically reconfigurable hardware designs. CoNoChi is designed for taking advantage of the partial dynamic reconfiguration capabilities of modern FPGAs and applies this feature to adapt the network structure to the location, number and size of currently configured hardware modules. The network consists of the minimal number of switches required. Switches can be added or removed from the network by a global control instance at runtime. Compared to common fixed Network-on-Chip structures, the CoNoChi architecture reduces the area requirements and latency of the network and eases the online placement of hardware modules. Two variants of CoNoChi are presented: one is based on a homogeneous hardware structure that is dynamically reconfigurable on logic block level, and the other one is adapted to the limited partial reconfiguration capabilities of Xilinx Virtex-II (Pro) FPGAs.

Original languageEnglish
Title of host publication2006 International Conference on Field Programmable Logic and Applications
Number of pages6
Publication date01.12.2006
Article number4100970
ISBN (Print)1-4244-0312-X
Publication statusPublished - 01.12.2006
Event2006 International Conference on Field Programmable Logic and Applications - Madrid, Spain
Duration: 28.08.200630.08.2006
Conference number: 72423


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