Abstract
This paper presents an approach for modeling the achievable speed-ups of FPGAs (Field Programmable Gate Arrays) or GPUs (Graphic Processing Units) as coprocessors in hybrid computing systems. The underlying computation model assumes that the coprocessors are separate devices and that their input and output data are transferred from and into the system's memory. The model considers all overheads involved when (sub-)tasks are performed on a coprocessor instead of the CPU. By means of a sample application the validity of the model is checked against measured values. In addition, the theoretical maximum speed-ups of two hybrid systems compared to an optimal single core CPU implementation are approximated. Using penalty factor PSEQas a measure to which degree a program cannot be fully parallelized due to data dependencies, a system with a Nvidia GTX 285 GPU achieves a speed-up of 2.7 times PSEQ, while for a single node of a Cray XD1 with a Xilinx Virtex4 LX160 the speed-up is about 1 times PSEQ.
Original language | English |
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Title of host publication | Architecture of Computing Systems -- ARCS 2012 |
Editors | Andreas Herkersdorf, Kay Römer, Uwe Brinkschulte |
Number of pages | 12 |
Volume | 7179 LNCS |
Place of Publication | Berlin, Heidelberg |
Publisher | Springer Berlin Heidelberg |
Publication date | 2012 |
Pages | 160-171 |
ISBN (Print) | 978-3-642-28292-8 |
ISBN (Electronic) | 978-3-642-28293-5 |
DOIs | |
Publication status | Published - 2012 |
Event | 25th International Conference on Architecture of Computing Systems - Munich, Germany Duration: 28.02.2012 → 02.03.2012 Conference number: 88635 |