An adaptive system-on-chip for network applications

Roman Koch, Thilo Pionteck, Carsten Albrecht, Erik Maehle


This paper presents the hardware architecture of DynaCORE, a dynamically reconfigurable system-on-chip for network applications. DynaCORE is an application specific coprocessor for offloading computationally intensive tasks from a network processor. The system-on-chip architecture is based on an adaptable network-on-chip which allows the dynamic replacement of hardware modules as well as the adaptation of the on-chip communication structure. The coprocessor leverages the active partial reconfiguration feature of modern FPGAs in order to adapt to shifting demand patterns. An embedded general-purpose processor core within the coprocessor runs software which manages the configurations of the device. With reference to a prototypical implementation targeting a Xilinx Virtex-II Pro FPGA, this paper focuses on on-chip communication issues. Topics include the integration of PowerPC processor cores into the configurable logic as well as the mode of operation of the network-on-chip.

Original languageEnglish
Title of host publicationProceedings 20th IEEE International Parallel & Distributed Processing Symposium
Publication date01.01.2006
Article number1639445
ISBN (Print)1-4244-0054-6
Publication statusPublished - 01.01.2006
Event20th IEEE International Parallel and Distributed Processing Symposium
- Rhodes Island, Greece
Duration: 25.04.200629.04.2006
Conference number: 114989


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