A SSE-Based Implementation of a Ray Tracer for the Comparision with Coprocessors in Hybrid Computing Systems

Volker Hampel; Erik Maehle

A SSE-Based Implementation of a Ray Tracer for the Comparision with Coprocessors in Hybrid Computing Systems

Institute of Computer Engineering

Abstract

: In this paper we present and discuss our efforts to accelerate a sample application by using the Streaming SIMD Extensions (SSE) to the x64 instruction set. Several approaches to their integration into the source code are tested and evaluated against each other. They are assembler intrinsics, the initial source code combined with different compiler flags, and enhanced code for better SSE inference. Their performances are compared to benchmarks from two hybrid computing systems, which use a Field Programmable Gate Array (FPGA) and a Graphics Processing Unit (GPU), respectively. As the interfaces to manipulated/accelerated code sections are the same in all cases, comparability always is maintained.

Original language	English
Pages	131-140
Number of pages	10
Publication status	Published - 2011
Event	24th PARS - Workshop on Parallel Systems and Algorithms - Rüschlikon, Switzerland Duration: 26.05.2011 → 27.05.2011

Conference

Conference	24th PARS - Workshop on Parallel Systems and Algorithms
Country/Territory	Switzerland
City	Rüschlikon
Period	26.05.11 → 27.05.11

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 9 Industry, Innovation, and Infrastructure

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https://dl.gi.de/bitstream/handle/20.500.12116/8561/40731_2014_Article_BF03341992.pdf?sequence=1&isAllowed=y

Cite this

@conference{3872f26c7a964af8913fab582482dfb9,

title = "A SSE-Based Implementation of a Ray Tracer for the Comparision with Coprocessors in Hybrid Computing Systems",

abstract = ": In this paper we present and discuss our efforts to accelerate a sample application by using the Streaming SIMD Extensions (SSE) to the x64 instruction set. Several approaches to their integration into the source code are tested and evaluated against each other. They are assembler intrinsics, the initial source code combined with different compiler flags, and enhanced code for better SSE inference. Their performances are compared to benchmarks from two hybrid computing systems, which use a Field Programmable Gate Array (FPGA) and a Graphics Processing Unit (GPU), respectively. As the interfaces to manipulated/accelerated code sections are the same in all cases, comparability always is maintained.",

author = "Volker Hampel and Erik Maehle",

year = "2011",

language = "English",

pages = "131--140",

note = " 24th PARS - Workshop on Parallel Systems and Algorithms ; Conference date: 26-05-2011 Through 27-05-2011",

}

Hampel, V & Maehle, E 2011, 'A SSE-Based Implementation of a Ray Tracer for the Comparision with Coprocessors in Hybrid Computing Systems', Paper presented at 24th PARS - Workshop on Parallel Systems and Algorithms, Rüschlikon, Switzerland, 26.05.11 - 27.05.11 pp. 131-140. <https://dl.gi.de/bitstream/handle/20.500.12116/8561/40731_2014_Article_BF03341992.pdf?sequence=1&isAllowed=y>

TY - CONF

T1 - A SSE-Based Implementation of a Ray Tracer for the Comparision with Coprocessors in Hybrid Computing Systems

AU - Hampel, Volker

AU - Maehle, Erik

PY - 2011

Y1 - 2011

N2 - : In this paper we present and discuss our efforts to accelerate a sample application by using the Streaming SIMD Extensions (SSE) to the x64 instruction set. Several approaches to their integration into the source code are tested and evaluated against each other. They are assembler intrinsics, the initial source code combined with different compiler flags, and enhanced code for better SSE inference. Their performances are compared to benchmarks from two hybrid computing systems, which use a Field Programmable Gate Array (FPGA) and a Graphics Processing Unit (GPU), respectively. As the interfaces to manipulated/accelerated code sections are the same in all cases, comparability always is maintained.

AB - : In this paper we present and discuss our efforts to accelerate a sample application by using the Streaming SIMD Extensions (SSE) to the x64 instruction set. Several approaches to their integration into the source code are tested and evaluated against each other. They are assembler intrinsics, the initial source code combined with different compiler flags, and enhanced code for better SSE inference. Their performances are compared to benchmarks from two hybrid computing systems, which use a Field Programmable Gate Array (FPGA) and a Graphics Processing Unit (GPU), respectively. As the interfaces to manipulated/accelerated code sections are the same in all cases, comparability always is maintained.

M3 - Conference Papers

SP - 131

EP - 140

T2 - 24th PARS - Workshop on Parallel Systems and Algorithms

Y2 - 26 May 2011 through 27 May 2011

ER -

A SSE-Based Implementation of a Ray Tracer for the Comparision with Coprocessors in Hybrid Computing Systems

Abstract

Conference

UN SDGs

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Cite this