A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip

J. M. Joseph, Sven Wrieden, C. Blochwitz, A. García-Oritz, T. Pionteck


We present a comprehensive simulation environment for design space exploration in Asymmetric 3D-Networks-on-chip (A-3D-NoCs) covering the heterogeneity in 3D-System-on-chips (3D-SoCs). A challenging aspect of A-3D-NoC design is the consideration of interwoven parameters of the communication infrastructure and characteristics of the manufacturing technologies. Thus, simultaneous evaluation of multiple design metrics is mandatory. Our simulation environment consists of three parts. First, it comprises a NoC simulator that supports a multitude of different manufacturing technologies, router architectures, and network topologies within a single design. As a key feature, the NoC and technologies parameters per chip layer are fully configurable during simulation runtime permitting flexible and fast evaluation. Second, a central reporting tool facilitates system analysis on different abstraction levels. Third, the evolution tool provides various synthetic and real-world based benchmarks. Thus, our tool allows for an incremental approach to systematically explore the A-3D-NoC's design space.
Original languageEnglish
Title of host publication2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
Number of pages8
Publication date01.06.2016
Article number7533908
ISBN (Print)978-1-5090-2521-3
ISBN (Electronic)978-1-5090-2520-6
Publication statusPublished - 01.06.2016
Event11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip - Tallinn, Estonia
Duration: 27.06.201629.06.2016
Conference number: 123201


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