This paper describes a lightweight framework for prototyping runtime reconfigurable systems in a Xilinx Virtex-II Pro FPGA. The framework provides a reconfiguration and control infrastructure that allows components of the prototype system to be modified or exchanged at runtime by means of partial reconfiguration of the FPGA. The system state may be monitored and influenced by a programmable controller which is part of the framework. The area over-head of the framework is kept low by efficiently utilising the two hard-wired PowerPC processor cores inside the FPGA while avoiding the use of resource-intense bus structures. Specific lean input/output modules are used with the one processor core while the other implements a Xilinx UltraController-II based design.
|Title of host publication
|18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP '07)
|Number of pages
|Published - 25.09.2007
|18th IEEE/IFIP International Workshop on Rapid System Prototyping - Porto alegre, Brazil
Duration: 28.05.2007 → 30.05.2007
Conference number: 70234