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A Large-Scale Hardware Timer Manager
Silvio Dragone, Andreas C. Döring, Rainer Hagenau
Institute of Computer Engineering
IBM Zurich Research Laboratory
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Computer Science
Coprocessor
100%
Hardware Timer
100%
Detection
50%
Internet
50%
Data Structure
50%
Memory Access
50%
Processor Cache
50%
Network Protocols
50%
External Memory
50%
SystemC
50%
Latency Operation
50%
Network Processing Unit
50%
Multiplicity
50%