A Large-Scale Hardware Timer Manager

Timers are used throughout in network protocols, particularly for packet loss detection and for connec-tion management. Thus, at least one timer is used per connection. Internet servers and gateways need to serve several thousands of simultaneously open con-nections, therefore a multiplicity of timers have to be managed simultaneously. To achieve scalable timer management, we present a large-scale hardware timer manager that can be implemented as a coprocessor in any network processing unit. This coprocessor uses on-and off-chip memory to handle the timers. The on-chip memory functions like a processor cache to reduce the number of external memory accesses and therefore, to decrease operation latency. To sort the timers according to their expiration time, the data structure of the timer manager is based on the d-heap structure. We have simulated the model in SystemC to measure the performance of the timer operations: start, stop and expire. In this paper present a hard-ware concept for a large-scale timer manager and we discuss the simulation results, to show its efficiency.