A Dynamically Reconfigurable Packet-Switched Network-on-Chip

Thilo Pionteck; Carsten Albrecht; Roman Koch

doi:10.1109/DATE.2006.244035

A Dynamically Reconfigurable Packet-Switched Network-on-Chip

Thilo Pionteck, Carsten Albrecht, Roman Koch

Institute of Computer Engineering

Abstract

This paper presents the design of an adaptable NoC for FPGA based dynamically reconfigurable SoCs. At runtime, switches can be added or removed from the network, allowing to adapt the NoC to the number, size and location of currently configured hardware modules. By using dynamic routing tables, reconfiguration can be done without stopping or stalling the NoC. The proposed architecture avoids the limitations of bus-based interconnection schemes which are often applied in partially dynamically reconfigurable FPGA designs.

Original language	English
Title of host publication	Proceedings of the Design Automation & Test in Europe Conference
Publisher	IEEE
Publication date	01.12.2006
Article number	1656864
ISBN (Print)	3-9810801-1-4
DOIs	https://doi.org/10.1109/DATE.2006.244035
Publication status	Published - 01.12.2006
Event	Design, Automation and Test in Europe - Munich , Germany Duration: 06.03.2006 → 10.03.2006 Conference number: 69442

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AB - This paper presents the design of an adaptable NoC for FPGA based dynamically reconfigurable SoCs. At runtime, switches can be added or removed from the network, allowing to adapt the NoC to the number, size and location of currently configured hardware modules. By using dynamic routing tables, reconfiguration can be done without stopping or stalling the NoC. The proposed architecture avoids the limitations of bus-based interconnection schemes which are often applied in partially dynamically reconfigurable FPGA designs.

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A Dynamically Reconfigurable Packet-Switched Network-on-Chip

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