A Dynamically Reconfigurable Packet-Switched Network-on-Chip

Thilo Pionteck, Carsten Albrecht, Roman Koch


This paper presents the design of an adaptable NoC for FPGA based dynamically reconfigurable SoCs. At runtime, switches can be added or removed from the network, allowing to adapt the NoC to the number, size and location of currently configured hardware modules. By using dynamic routing tables, reconfiguration can be done without stopping or stalling the NoC. The proposed architecture avoids the limitations of bus-based interconnection schemes which are often applied in partially dynamically reconfigurable FPGA designs.

Original languageEnglish
Title of host publication Proceedings of the Design Automation & Test in Europe Conference
Publication date01.12.2006
Article number1656864
ISBN (Print)3-9810801-1-4
Publication statusPublished - 01.12.2006
EventDesign, Automation and Test in Europe - Munich , Germany
Duration: 06.03.200610.03.2006
Conference number: 69442


Dive into the research topics of 'A Dynamically Reconfigurable Packet-Switched Network-on-Chip'. Together they form a unique fingerprint.

Cite this