A cycle-accurate Network-on-Chip simulator with support for abstract task graph modeling

J. M. Joseph, T. Pionteck


This papers presents the design of a Network-on-Chip (NoC) simulator for design space exploration of router architectures. The simulator supports cycle-accurate router models and in addition allows the simulation of router architectures, which can adjust their processing according to the traffic type. Realistic traffic patterns are derived from task graph models of real-world applications that are simulated in parallel to the NoC at transaction level. Combining cycle-accurate router simulation and abstract task graph simulation circumvents the limitations of most NoC simulators, which either use synthetic traffic patterns or unrealistic and fixed router models. The proposed simulator architecture is presented in detail and its suitability is shown by means of a case study.
Original languageEnglish
Title of host publication2014 International Symposium on System-on-Chip (SoC)
Number of pages6
Publication date01.10.2014
Article number6972440
ISBN (Electronic)978-1-4799-6890-9
Publication statusPublished - 01.10.2014
Event2014 16th International Symposium on System-on-Chip - Tampere, Finland
Duration: 28.10.201429.10.2014
Conference number: 109511


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