Abstract
Today’s network processor utilize parallel processing in order to cope with the traffic growth and wire-speed of current and future network technologies. In this paper, we study two important parallel programming models for network processors: run to completion and pipelining. In particular, the packet flow of a standard network application, IPv4 Forwarding, through two examined network processors, IBM PowerNP NP4GS3 and Intel IXP1200, is reviewed and characterized in respect to their programming models. Based on a benchmark for PC-cluster SANs, their application throughput and latency for Gigabit Ethernet is investigated and compared to a commercial, ASIC-based switch. It is shown that in this scenario network processors can compete with hard-wired solutions.
| Original language | English |
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| Title of host publication | ARCS 2004 - Organic and Pervasive Computing, Workshops Proceedings, March 26, 2004, Augsburg, Germany |
| Number of pages | 10 |
| Volume | 41 |
| Publisher | Gesellschaft für Informatik, Bonn |
| Publication date | 2004 |
| Pages | 390-399 |
| ISBN (Print) | 3-88579-370-9 |
| Publication status | Published - 2004 |