A Comparison of Parallel Programming Models of Network Processors

Carsten Albrecht, Rainer Hagenau, Erik Maehle, Andreas C. Döring, Andreas Herkersdorf


Today’s network processor utilize parallel processing in order to cope with the traffic growth and wire-speed of current and future network technologies. In this paper, we study two important parallel programming models for network processors: run to completion and pipelining. In particular, the packet flow of a standard network application, IPv4 Forwarding, through two examined network processors, IBM PowerNP NP4GS3 and Intel IXP1200, is reviewed and characterized in respect to their programming models. Based on a benchmark for PC-cluster SANs, their application throughput and latency for Gigabit Ethernet is investigated and compared to a commercial, ASIC-based switch. It is shown that in this scenario network processors can compete with hard-wired solutions.
Original languageEnglish
Title of host publicationARCS 2004 - Organic and Pervasive Computing, Workshops Proceedings, March 26, 2004, Augsburg, Germany
Number of pages10
PublisherGesellschaft für Informatik, Bonn
Publication date2004
ISBN (Print)3-88579-370-9
Publication statusPublished - 2004


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