A bandwidth accurate, flexible and rapid simulating multi-HMC modeling tool

Derived by the demand for ever increasing computing performance, a steadily widening performance gap between memory and processor architectures has emerged. While attempting to mitigate the effects for processing systems that already face the exascale barrier and beyond, energy-efficient computing was identified as the critical topic to provide further scaling. Memory architectures, persistently known as slow, energy-hungry and cost-intensive, require novel findings to aid in increasing the energy efficiency as well as bandwidth. A quick fix for the performance aspect seems to be 3D stacking of such planar memories, that is available in the form of the High Bandwidth Memory (HBM) and the Hybrid Memory Cube (HMC). With the latter allowing to embed custom logic, novel non-von Neumann architectures can be accomplished, overcoming the performance gap while achieving a new path for scaling the computing performance. Considering the broad spectrum of custom logic that could be integrated into a mesh of HMCs, comprehensive modeling tools are required, enabling holistic design-space explorations for computing systems in breadth and depth. Fulfilling this demand, an HMC-modeling tool was implemented, providing rapid simulation of multiple interconnected HMCs that can run either in a functional or in a bandwidth-accurate mode. Since flexibility is a key for subsequent studies, the HMC-modeling tool is parameterizable whereas internal components can be adjusted.