Unifying Timer and Interrupt Management for an ARM-RISC-V-Heterogeneous Multi-Core

Marcel Eckert, Jan Haase, Bernd Klauer

Abstract

A timer and interrupt management infrastructure is essential for a computer system executing a preemptive operating system. This holds for single- and also for multicore systems. When it comes to OS-capable ISA-heterogeneous multicore systems (systems that include cores of different ISAs, which all are capable of executing an operating system) the different timer and interrupt infrastructures of the different system ISAs are still applicable. However, if reconfigurability is added on top of the ISA heterogeneity, meaning that the composition (number of individual cores) is runtime adaptable, the timer and interrupt management infrastructure needs to be reconsidered. In this paper, a unified timer and interrupt management scheme is deduced for a runtime adaptable, OS-capable, ISA-heterogeneous multi-core system, consisting of ARM and RISC-V cores, that are capable of executing Linux. This is done by analyzing/surveying the timer and interrupt management schemes of RISC-V and ARM systems. Finally this paper will show that RISC-V timer and interrupt management devices are suitable to also manage timers and interrupts for ARM based systems.

OriginalspracheEnglisch
TitelIECON 2020 The 46th Annual Conference of the IEEE Industrial Electronics Society
Seitenumfang8
Herausgeber (Verlag)IEEE
Erscheinungsdatum18.10.2020
Seiten2302-2309
Aufsatznummer9255193
ISBN (Print)978-1-7281-5415-2, 978-1-7281-5413-8
ISBN (elektronisch)978-1-7281-5414-5
DOIs
PublikationsstatusVeröffentlicht - 18.10.2020
Veranstaltung46th Annual Conference of the IEEE Industrial Electronics Society - Virtual, Singapore, Singapur
Dauer: 19.10.202021.10.2020
Konferenznummer: 165032

Fingerprint

Untersuchen Sie die Forschungsthemen von „Unifying Timer and Interrupt Management for an ARM-RISC-V-Heterogeneous Multi-Core“. Zusammen bilden sie einen einzigartigen Fingerprint.

Zitieren