RTeasy - An Algorithmic Design Environment on Register Transfer Level

Hagen Schendel; Carsten Albrecht; Erik Maehle

doi:10.1145/1275571.1275581

RTeasy - An Algorithmic Design Environment on Register Transfer Level

Hagen Schendel, Carsten Albrecht, Erik Maehle

Institut für Technische Informatik

Institute of Computer Engineering

Abstract

Current developer tools and HDLs for system design are powerful instruments and support a variety of abstraction levels but they are too complex for didactic purposes. This paper describes the RTeasy IDE, an algorithmic design environment on register transfer level that has been developed to provide a simple system-design tool for didactic purposes to be used e.g. in introductory courses in computer engineering and digital design. The RTeasy tool suite includes an HDL, a simulator and further design features. As an example, it is applied to the design flow of a shift-multiplier.

Originalsprache	Englisch
DOIs	https://doi.org/10.1145/1275571.1275581
Publikationsstatus	Veröffentlicht - 01.12.2004
Veranstaltung	2004 Workshop on Computer Architecture Education - Held in Conjunction with the 31st International Symposium on Computer Architecture - Munich, Deutschland Dauer: 19.06.2004 → 19.06.2004 Konferenznummer: 102980

Tagung, Konferenz, Kongress

Tagung, Konferenz, Kongress	2004 Workshop on Computer Architecture Education - Held in Conjunction with the 31st International Symposium on Computer Architecture
Kurztitel	WCAE 2004 and ISCA 2004
Land/Gebiet	Deutschland
Ort	Munich
Zeitraum	19.06.04 → 19.06.04

UN SDGs

Dieser Output leistet einen Beitrag zu folgendem(n) Ziel(en) für nachhaltige Entwicklung

SDG 9 – Industrie, Innovation und Infrastruktur

Dokumente

10.1145/1275571.1275581

Weitere Links

Link to Scopus

Zitieren

@conference{cb6a8ac116484c0a8f1d4fe2b0fe7b04,

title = "RTeasy - An Algorithmic Design Environment on Register Transfer Level",

abstract = "Current developer tools and HDLs for system design are powerful instruments and support a variety of abstraction levels but they are too complex for didactic purposes. This paper describes the RTeasy IDE, an algorithmic design environment on register transfer level that has been developed to provide a simple system-design tool for didactic purposes to be used e.g. in introductory courses in computer engineering and digital design. The RTeasy tool suite includes an HDL, a simulator and further design features. As an example, it is applied to the design flow of a shift-multiplier.",

author = "Hagen Schendel and Carsten Albrecht and Erik Maehle",

year = "2004",

month = dec,

day = "1",

doi = "10.1145/1275571.1275581",

language = "English",

note = "2004 Workshop on Computer Architecture Education - Held in Conjunction with the 31st International Symposium on Computer Architecture, WCAE 2004 and ISCA 2004 ; Conference date: 19-06-2004 Through 19-06-2004",

}

RTeasy - An Algorithmic Design Environment on Register Transfer Level. / Schendel, Hagen; Albrecht, Carsten; Maehle, Erik.
2004. Beitrag in 2004 Workshop on Computer Architecture Education - Held in Conjunction with the 31st International Symposium on Computer Architecture, Munich, Bayern, Deutschland.

Publikation: Konferenzbeiträge › Konferenzpapiere › Begutachtung

TY - CONF

T1 - RTeasy - An Algorithmic Design Environment on Register Transfer Level

AU - Schendel, Hagen

AU - Albrecht, Carsten

AU - Maehle, Erik

N1 - Conference code: 102980

PY - 2004/12/1

Y1 - 2004/12/1

N2 - Current developer tools and HDLs for system design are powerful instruments and support a variety of abstraction levels but they are too complex for didactic purposes. This paper describes the RTeasy IDE, an algorithmic design environment on register transfer level that has been developed to provide a simple system-design tool for didactic purposes to be used e.g. in introductory courses in computer engineering and digital design. The RTeasy tool suite includes an HDL, a simulator and further design features. As an example, it is applied to the design flow of a shift-multiplier.

AB - Current developer tools and HDLs for system design are powerful instruments and support a variety of abstraction levels but they are too complex for didactic purposes. This paper describes the RTeasy IDE, an algorithmic design environment on register transfer level that has been developed to provide a simple system-design tool for didactic purposes to be used e.g. in introductory courses in computer engineering and digital design. The RTeasy tool suite includes an HDL, a simulator and further design features. As an example, it is applied to the design flow of a shift-multiplier.

UR - https://www.scopus.com/pages/publications/84897743433

U2 - 10.1145/1275571.1275581

DO - 10.1145/1275571.1275581

M3 - Conference Papers

T2 - 2004 Workshop on Computer Architecture Education - Held in Conjunction with the 31st International Symposium on Computer Architecture

Y2 - 19 June 2004 through 19 June 2004

ER -

RTeasy - An Algorithmic Design Environment on Register Transfer Level

Abstract

Tagung, Konferenz, Kongress

UN SDGs

Dokumente

Weitere Links

Fingerprint

Zitieren