On the design of a dynamically reconfigurable function-unit for error detection and correction

Thilo Pionteck; Thomas Stiefmeier; Thorsten Staake; Manfred Glesner

doi:10.1007/978-0-387-73661-7_18

On the design of a dynamically reconfigurable function-unit for error detection and correction

Thilo Pionteck^*, Thomas Stiefmeier, Thorsten Staake, Manfred Glesner

^*Korrespondierende/r Autor/-in für diese Arbeit

Institut für Technische Informatik

Abstract

This paper presents the design of a function-specific dynamically reconfigurable architecture for error detection and error correction. The function-unit is integrated in a pipelined 32 bit RISC processor and provides full hardware support for encoding and decoding of Reed-Solomon Codes with different code lengths as well as error detection methods like bit-parallel Cyclic Redundancy Check codes computation. The architecture is designed and optimized for the usage in the medium access control layer of mobile wireless communication systems and provides simultaneously hardware support for control-flow and data-flow oriented tasks.

Originalsprache	Englisch
Titel	Vlsi-Soc : From Systems To Silicon: Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth
Seitenumfang	15
Band	240
Erscheinungsort	Boston, MA
Herausgeber (Verlag)	Springer Verlag
Erscheinungsdatum	24.09.2007
Seiten	283-297
ISBN (Print)	978-0-387-73660-0
ISBN (elektronisch)	978-0-387-73661-7
DOIs	https://doi.org/10.1007/978-0-387-73661-7_18
Publikationsstatus	Veröffentlicht - 24.09.2007

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10.1007/978-0-387-73661-7_18

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Pionteck, T., Stiefmeier, T., Staake, T., & Glesner, M. (2007). On the design of a dynamically reconfigurable function-unit for error detection and correction. in Vlsi-Soc: From Systems To Silicon: Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth (Band 240, S. 283-297). (IFIP International Federation for Information Processing; Band 240). Springer Verlag. https://doi.org/10.1007/978-0-387-73661-7_18

Pionteck, Thilo ; Stiefmeier, Thomas ; Staake, Thorsten et al. / On the design of a dynamically reconfigurable function-unit for error detection and correction. Vlsi-Soc: From Systems To Silicon: Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth. Band 240 Boston, MA : Springer Verlag, 2007. S. 283-297 (IFIP International Federation for Information Processing).

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abstract = "This paper presents the design of a function-specific dynamically reconfigurable architecture for error detection and error correction. The function-unit is integrated in a pipelined 32 bit RISC processor and provides full hardware support for encoding and decoding of Reed-Solomon Codes with different code lengths as well as error detection methods like bit-parallel Cyclic Redundancy Check codes computation. The architecture is designed and optimized for the usage in the medium access control layer of mobile wireless communication systems and provides simultaneously hardware support for control-flow and data-flow oriented tasks.",

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Pionteck, T, Stiefmeier, T, Staake, T & Glesner, M 2007, On the design of a dynamically reconfigurable function-unit for error detection and correction. in Vlsi-Soc: From Systems To Silicon: Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth. Bd. 240, IFIP International Federation for Information Processing, Bd. 240, Springer Verlag, Boston, MA, S. 283-297. https://doi.org/10.1007/978-0-387-73661-7_18

On the design of a dynamically reconfigurable function-unit for error detection and correction. / Pionteck, Thilo; Stiefmeier, Thomas; Staake, Thorsten et al.
Vlsi-Soc: From Systems To Silicon: Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth. Band 240 Boston, MA: Springer Verlag, 2007. S. 283-297 (IFIP International Federation for Information Processing; Band 240).

Publikation: Kapitel in Büchern/Berichten/Konferenzbänden › Konferenzbeitrag › Begutachtung

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AU - Glesner, Manfred

PY - 2007/9/24

Y1 - 2007/9/24

N2 - This paper presents the design of a function-specific dynamically reconfigurable architecture for error detection and error correction. The function-unit is integrated in a pipelined 32 bit RISC processor and provides full hardware support for encoding and decoding of Reed-Solomon Codes with different code lengths as well as error detection methods like bit-parallel Cyclic Redundancy Check codes computation. The architecture is designed and optimized for the usage in the medium access control layer of mobile wireless communication systems and provides simultaneously hardware support for control-flow and data-flow oriented tasks.

AB - This paper presents the design of a function-specific dynamically reconfigurable architecture for error detection and error correction. The function-unit is integrated in a pipelined 32 bit RISC processor and provides full hardware support for encoding and decoding of Reed-Solomon Codes with different code lengths as well as error detection methods like bit-parallel Cyclic Redundancy Check codes computation. The architecture is designed and optimized for the usage in the medium access control layer of mobile wireless communication systems and provides simultaneously hardware support for control-flow and data-flow oriented tasks.

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U2 - 10.1007/978-0-387-73661-7_18

DO - 10.1007/978-0-387-73661-7_18

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AN - SCOPUS:34548770724

SN - 978-0-387-73660-0

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T3 - IFIP International Federation for Information Processing

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PB - Springer Verlag

CY - Boston, MA

ER -

Pionteck T, Stiefmeier T, Staake T, Glesner M. On the design of a dynamically reconfigurable function-unit for error detection and correction. in Vlsi-Soc: From Systems To Silicon: Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth. Band 240. Boston, MA: Springer Verlag. 2007. S. 283-297. (IFIP International Federation for Information Processing). doi: 10.1007/978-0-387-73661-7_18

On the design of a dynamically reconfigurable function-unit for error detection and correction

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