Latency Reduction of Selected Data Streams in Network-on-Chips for Adaptive Manycore Systems

This paper reviews Network-on-Chip architectures with prioritization of selected data streams targeting runtime reconfigurable manycore systems. The common idea of these architectures is to minimize the latency of selected packet transmissions by either bypassing or parallelizing processing stages in routers or by using dedicated links bypassing complete routers. Potential classes of selected data streams are latency critical messages, i.e. cache accesses in multiprocessor systems, or systems with semi-static data streams, i.e. systems in which the same components continuously exchange data for a longer period. The review categorizes the diverse architectures and evaluates their pros and cons in terms of universality, hardware efficiency and support of changing traffic patterns.