Hardware-accelerated pose estimation for embedded systems using Vivado HLS

J. M. Joseph; T. Winker; K. Ehlers; C. Blochwitz; T. Pionteck

doi:10.1109/ReConFig.2016.7857173

Hardware-accelerated pose estimation for embedded systems using Vivado HLS

J. M. Joseph, T. Winker, K. Ehlers, C. Blochwitz, T. Pionteck

Institut für Technische Informatik

Abstract

The focus of this work is to facilitate pose estimation and, thus, gesture recognition for embedded systems, although these are tasks with high computational performance requirements. Therefore, an existing pose estimation algorithm is optimized for Xilinx High Level Synthesis (HLS). The resulting hardware acceleration cores are compared for different optimizations and, finally, we propose a hardware/software system design for a Xilinx Zynq Zedboard. Using this method, we achieve a speedup of 1.6 in comparison to a software solution on the ARM processor and, thus, facilitate hand tracking for embedded systems with low power consumption.

Originalsprache	Englisch
Titel	2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig)
Seitenumfang	7
Herausgeber (Verlag)	IEEE
Erscheinungsdatum	01.11.2016
Seiten	1-7
Aufsatznummer	126407
ISBN (Print)	978-1-5090-3708-7
ISBN (elektronisch)	978-1-5090-3707-0
DOIs	https://doi.org/10.1109/ReConFig.2016.7857173
Publikationsstatus	Veröffentlicht - 01.11.2016
Veranstaltung	2016 International Conference on Reconfigurable Computing and FPGAs - Cancun, Mexico Dauer: 30.11.2016 → 02.12.2016 Konferenznummer: 126407

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@inproceedings{0940357cf275457594e6d38b871117fb,

title = "Hardware-accelerated pose estimation for embedded systems using Vivado HLS",

abstract = "The focus of this work is to facilitate pose estimation and, thus, gesture recognition for embedded systems, although these are tasks with high computational performance requirements. Therefore, an existing pose estimation algorithm is optimized for Xilinx High Level Synthesis (HLS). The resulting hardware acceleration cores are compared for different optimizations and, finally, we propose a hardware/software system design for a Xilinx Zynq Zedboard. Using this method, we achieve a speedup of 1.6 in comparison to a software solution on the ARM processor and, thus, facilitate hand tracking for embedded systems with low power consumption.",

author = "Joseph, {J. M.} and T. Winker and K. Ehlers and C. Blochwitz and T. Pionteck",

year = "2016",

month = nov,

day = "1",

doi = "10.1109/ReConFig.2016.7857173",

language = "English",

isbn = "978-1-5090-3708-7",

series = "IEEE Proceedings",

publisher = "IEEE",

pages = "1--7",

booktitle = "2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig)",

note = "2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016 ; Conference date: 30-11-2016 Through 02-12-2016",

}

Joseph, JM, Winker, T, Ehlers, K , Blochwitz, C & Pionteck, T 2016, Hardware-accelerated pose estimation for embedded systems using Vivado HLS. in 2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig)., 126407, IEEE Proceedings, IEEE, S. 1-7, 2016 International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, 30.11.16. https://doi.org/10.1109/ReConFig.2016.7857173

TY - GEN

T1 - Hardware-accelerated pose estimation for embedded systems using Vivado HLS

AU - Joseph, J. M.

AU - Winker, T.

AU - Ehlers, K.

AU - Blochwitz, C.

AU - Pionteck, T.

N1 - Conference code: 126407

PY - 2016/11/1

Y1 - 2016/11/1

N2 - The focus of this work is to facilitate pose estimation and, thus, gesture recognition for embedded systems, although these are tasks with high computational performance requirements. Therefore, an existing pose estimation algorithm is optimized for Xilinx High Level Synthesis (HLS). The resulting hardware acceleration cores are compared for different optimizations and, finally, we propose a hardware/software system design for a Xilinx Zynq Zedboard. Using this method, we achieve a speedup of 1.6 in comparison to a software solution on the ARM processor and, thus, facilitate hand tracking for embedded systems with low power consumption.

AB - The focus of this work is to facilitate pose estimation and, thus, gesture recognition for embedded systems, although these are tasks with high computational performance requirements. Therefore, an existing pose estimation algorithm is optimized for Xilinx High Level Synthesis (HLS). The resulting hardware acceleration cores are compared for different optimizations and, finally, we propose a hardware/software system design for a Xilinx Zynq Zedboard. Using this method, we achieve a speedup of 1.6 in comparison to a software solution on the ARM processor and, thus, facilitate hand tracking for embedded systems with low power consumption.

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DO - 10.1109/ReConFig.2016.7857173

M3 - Conference contribution

SN - 978-1-5090-3708-7

T3 - IEEE Proceedings

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BT - 2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig)

PB - IEEE

T2 - 2016 International Conference on Reconfigurable Computing and FPGAs

Y2 - 30 November 2016 through 2 December 2016

ER -

Hardware-accelerated pose estimation for embedded systems using Vivado HLS

Abstract

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