Experiences with a FPGA-based Reed/Solomon Encoding Coprocessor

Volker Hampel; Peter Sobe; Erik Maehle

doi:10.1109/DSD.2007.4341453

Experiences with a FPGA-based Reed/Solomon Encoding Coprocessor

Volker Hampel, Peter Sobe, Erik Maehle

Institut für Technische Informatik

Abstract

In this paper we present an implementation of a Reed/Solomon (R/S) coprocessor to be used on a hybrid computing system, which combines general purpose CPUs with FPGAs. The coprocessor accelerates the encoding of user data to be stored block-wise on a distributed, failure tolerant storage system. We document design constraints and their impact on the resulting architecture. Measurements are presented to characterize the performance of the coprocessor in terms of computation bandwidth, latency, and the hardware-software interaction. For comparison, software based R/S encoding implementations are presented and evaluated as well. Finally, the performance of the hardware accelerated encoding is compared to a software based system.

Originalsprache	Englisch
Titel	10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)
Seitenumfang	8
Herausgeber (Verlag)	IEEE
Erscheinungsdatum	01.12.2007
Seiten	77-84
Aufsatznummer	4341453
ISBN (Print)	978-0-7695-2978-X, 978-0-7695-2978-3
DOIs	https://doi.org/10.1109/DSD.2007.4341453
Publikationsstatus	Veröffentlicht - 01.12.2007
Veranstaltung	10th Euromicro Conference on Digital System Design Architectures, Methods and Tools - Lübeck, Deutschland Dauer: 29.08.2007 → 31.08.2007 Konferenznummer: 72733

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title = "Experiences with a FPGA-based Reed/Solomon Encoding Coprocessor",

abstract = "In this paper we present an implementation of a Reed/Solomon (R/S) coprocessor to be used on a hybrid computing system, which combines general purpose CPUs with FPGAs. The coprocessor accelerates the encoding of user data to be stored block-wise on a distributed, failure tolerant storage system. We document design constraints and their impact on the resulting architecture. Measurements are presented to characterize the performance of the coprocessor in terms of computation bandwidth, latency, and the hardware-software interaction. For comparison, software based R/S encoding implementations are presented and evaluated as well. Finally, the performance of the hardware accelerated encoding is compared to a software based system.",

author = "Volker Hampel and Peter Sobe and Erik Maehle",

year = "2007",

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doi = "10.1109/DSD.2007.4341453",

language = "English",

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note = "10th Euromicro Conference on Digital System Design Architectures, Methods and Tools <br/>, DSD 2007 ; Conference date: 29-08-2007 Through 31-08-2007",

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Hampel, V, Sobe, P & Maehle, E 2007, Experiences with a FPGA-based Reed/Solomon Encoding Coprocessor. in 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)., 4341453, IEEE Proceedings, IEEE, S. 77-84, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
, Lübeck, Schleswig-Holstein, Deutschland, 29.08.07. https://doi.org/10.1109/DSD.2007.4341453

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AU - Hampel, Volker

AU - Sobe, Peter

AU - Maehle, Erik

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PY - 2007/12/1

Y1 - 2007/12/1

N2 - In this paper we present an implementation of a Reed/Solomon (R/S) coprocessor to be used on a hybrid computing system, which combines general purpose CPUs with FPGAs. The coprocessor accelerates the encoding of user data to be stored block-wise on a distributed, failure tolerant storage system. We document design constraints and their impact on the resulting architecture. Measurements are presented to characterize the performance of the coprocessor in terms of computation bandwidth, latency, and the hardware-software interaction. For comparison, software based R/S encoding implementations are presented and evaluated as well. Finally, the performance of the hardware accelerated encoding is compared to a software based system.

AB - In this paper we present an implementation of a Reed/Solomon (R/S) coprocessor to be used on a hybrid computing system, which combines general purpose CPUs with FPGAs. The coprocessor accelerates the encoding of user data to be stored block-wise on a distributed, failure tolerant storage system. We document design constraints and their impact on the resulting architecture. Measurements are presented to characterize the performance of the coprocessor in terms of computation bandwidth, latency, and the hardware-software interaction. For comparison, software based R/S encoding implementations are presented and evaluated as well. Finally, the performance of the hardware accelerated encoding is compared to a software based system.

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BT - 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)

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Experiences with a FPGA-based Reed/Solomon Encoding Coprocessor

Abstract

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