DynaCORE-dynamically reconfigurable coprocessor for network processors

Carsten Albrecht; Jürgen Foag; Roman Koch; Erik Maehle; Thilo Pionteck

doi:10.1007/978-90-481-3485-4_16

DynaCORE-dynamically reconfigurable coprocessor for network processors

Carsten Albrecht, Jürgen Foag, Roman Koch, Erik Maehle, Thilo Pionteck

Institut für Technische Informatik

3 Zitate (Scopus)

Abstract

This chapter presents DynaCORE, a dynamically reconfigurable coprocessor architecture for network processors. The architecture takes over computationally intensive tasks from network processors and provides dynamically exchangeable hardware assists for complex payload processing. According to the actual traffic profile, DynaCORE autonomously determines an optimal set of hardware assists. The hardware assists reside in a grid of exchangeable tiles which are connected by a runtime adaptable network-on-chip. System simulation, hardware architecture as well as reconfiguration management strategies are presented within this chapter.

Originalsprache	Englisch
Titel	Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications
Seitenumfang	20
Herausgeber (Verlag)	Springer Netherlands
Erscheinungsdatum	01.12.2010
Seiten	335-354
ISBN (Print)	978-90-481-3484-7
ISBN (elektronisch)	978-90-481-3485-4
DOIs	https://doi.org/10.1007/978-90-481-3485-4_16
Publikationsstatus	Veröffentlicht - 01.12.2010

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DynaCORE-dynamically reconfigurable coprocessor for network processors

Abstract

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