Communication Architectures for Dynamically Reconfigurable FPGA Designs

Thilo Pionteck; Carsten Albrecht; Roman Koch; Erik Maehle; Michael Hübner; Jürgen Becker

doi:10.1109/IPDPS.2007.370364

Communication Architectures for Dynamically Reconfigurable FPGA Designs

Thilo Pionteck, Carsten Albrecht, Roman Koch, Erik Maehle, Michael Hübner, Jürgen Becker

Institut für Technische Informatik

16 Zitate (Scopus)

Abstract

This paper gives a survey of communication architectures which allow for dynamically exchangeable hardware modules. Four different architectures are compared in terms of reconfiguration capabilities, performance, flexibility and hardware requirements. A set of parameters for the classification of the different communication architectures is presented and the pro and cons of each architecture are elaborated. The analysis takes a minimal communication system for connecting four hardware modules as a common basis for the comparison of the diverse data given in the papers on the different architectures.

Originalsprache	Englisch
Titel	2007 IEEE International Parallel and Distributed Processing Symposium
Seitenumfang	8
Herausgeber (Verlag)	IEEE
Erscheinungsdatum	24.09.2007
Seiten	1-8
Aufsatznummer	4228092
ISBN (Print)	1-4244-0909-8, 1-4244-0910-1
DOIs	https://doi.org/10.1109/IPDPS.2007.370364
Publikationsstatus	Veröffentlicht - 24.09.2007
Veranstaltung	21st International Parallel and Distributed Processing Symposium - Long Beach, USA / Vereinigte Staaten Dauer: 26.03.2007 → 30.03.2007 Konferenznummer: 70236

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10.1109/IPDPS.2007.370364

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title = "Communication Architectures for Dynamically Reconfigurable FPGA Designs",

abstract = "This paper gives a survey of communication architectures which allow for dynamically exchangeable hardware modules. Four different architectures are compared in terms of reconfiguration capabilities, performance, flexibility and hardware requirements. A set of parameters for the classification of the different communication architectures is presented and the pro and cons of each architecture are elaborated. The analysis takes a minimal communication system for connecting four hardware modules as a common basis for the comparison of the diverse data given in the papers on the different architectures.",

author = "Thilo Pionteck and Carsten Albrecht and Roman Koch and Erik Maehle and Michael H{\"u}bner and J{\"u}rgen Becker",

year = "2007",

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language = "English",

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series = "International Parallel and Distributed Processing Symposium",

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booktitle = "2007 IEEE International Parallel and Distributed Processing Symposium",

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Pionteck, T, Albrecht, C, Koch, R, Maehle, E, Hübner, M & Becker, J 2007, Communication Architectures for Dynamically Reconfigurable FPGA Designs. in 2007 IEEE International Parallel and Distributed Processing Symposium., 4228092, International Parallel and Distributed Processing Symposium, IEEE, S. 1-8, 21st International Parallel and Distributed Processing Symposium , Long Beach, California, USA / Vereinigte Staaten, 26.03.07. https://doi.org/10.1109/IPDPS.2007.370364

Communication Architectures for Dynamically Reconfigurable FPGA Designs. / Pionteck, Thilo; Albrecht, Carsten; Koch, Roman et al.
2007 IEEE International Parallel and Distributed Processing Symposium. IEEE, 2007. S. 1-8 4228092 (International Parallel and Distributed Processing Symposium).

Publikation: Kapitel in Büchern/Berichten/Konferenzbänden › Konferenzbeitrag › Begutachtung

TY - GEN

T1 - Communication Architectures for Dynamically Reconfigurable FPGA Designs

AU - Pionteck, Thilo

AU - Albrecht, Carsten

AU - Koch, Roman

AU - Maehle, Erik

AU - Hübner, Michael

AU - Becker, Jürgen

N1 - Conference code: 70236

PY - 2007/9/24

Y1 - 2007/9/24

N2 - This paper gives a survey of communication architectures which allow for dynamically exchangeable hardware modules. Four different architectures are compared in terms of reconfiguration capabilities, performance, flexibility and hardware requirements. A set of parameters for the classification of the different communication architectures is presented and the pro and cons of each architecture are elaborated. The analysis takes a minimal communication system for connecting four hardware modules as a common basis for the comparison of the diverse data given in the papers on the different architectures.

AB - This paper gives a survey of communication architectures which allow for dynamically exchangeable hardware modules. Four different architectures are compared in terms of reconfiguration capabilities, performance, flexibility and hardware requirements. A set of parameters for the classification of the different communication architectures is presented and the pro and cons of each architecture are elaborated. The analysis takes a minimal communication system for connecting four hardware modules as a common basis for the comparison of the diverse data given in the papers on the different architectures.

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U2 - 10.1109/IPDPS.2007.370364

DO - 10.1109/IPDPS.2007.370364

M3 - Conference contribution

SN - 1-4244-0909-8

SN - 1-4244-0910-1

T3 - International Parallel and Distributed Processing Symposium

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BT - 2007 IEEE International Parallel and Distributed Processing Symposium

PB - IEEE

T2 - 21st International Parallel and Distributed Processing Symposium

Y2 - 26 March 2007 through 30 March 2007

ER -

Communication Architectures for Dynamically Reconfigurable FPGA Designs

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