Synthesizing hardware from a Hardware Description Language (HDL) for Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs) is very important today because many companies produce ASICs or use FPGAs for prototyping or High Performance Computing (HPC). Although, the synthesis, mapping and routing processes are well understood and good covered by research, some challenges in the operation of these processes exist, such as easy design space exploration, commercial license management, and different software version support which are not focus of research yet. This paper addresses these challenges by proposing the outsourcing of the whole hardware synthesis process into the cloud. A complete cloud-based synthesis service is presented consisting out of a command line client to deploy a synthesis process into the cloud, a remote web-service to schedule synthesis jobs within a cluster of servers or virtual machines, and a control webservice on each of these machines to start and stop the synthesis process. This service is evaluated against the standard local synthesis flow.
|Titel||IECON 2016 - 42nd Annual Conference of the IEEE Industrial Electronics Society|
|Publikationsstatus||Veröffentlicht - 01.10.2016|
|Veranstaltung||42nd Conference of the Industrial Electronics Society - Palazzo dei Congressi Florence, Florence, Italien|
Dauer: 24.10.2016 → 27.10.2016