Automated composition and execution of hardware-accelerated operator graphs

S. Werner, D. Heinrich, S. Groppe, C. Blochwitz, T. Pionteck, Jannik Piper, Rico Backasch

Abstract

In this paper, we present the fully automated composition and execution of Semantic Web queries within a hardware/software system which uses a Field Programmable Gate Array (FPGA) as an accelerator. The presented approach allows to write a query in the database's front-end, transparently executes all steps to retrieve a configuration suitable for the FPGA which represents the given query, and obtains the result by evaluating the query on the FPGA. In order to obtain a runtime-reconfigurable framework we define a static and a dynamic partition. The dynamic partition itself is composed by using a predefined query template and a pool of operators. The operators of the given query are written automatically into the template and connected accordingly. After reconfiguration of the FPGA the host system supplies the initial data to the FPGA which computes the final result and sends it back to the host system to be displayed to the user or application. The evaluation shows that not all queries may take benefit from a dedicated hardware-accelerator but shows promising speedup for complex queries.
OriginalspracheEnglisch
Titel2015 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
Seitenumfang8
Herausgeber (Verlag)IEEE
Erscheinungsdatum01.06.2015
Seiten1-8
Aufsatznummer7238078
ISBN (Print)978-1-4673-7941-0
ISBN (elektronisch)978-1-4673-7942-7
DOIs
PublikationsstatusVeröffentlicht - 01.06.2015
Veranstaltung2015 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) - Bremen, Deutschland
Dauer: 29.06.201501.07.2015

Strategische Forschungsbereiche und Zentren

  • Querschnittsbereich: Intelligente Systeme
  • Zentren: Zentrum für Künstliche Intelligenz Lübeck (ZKIL)

DFG-Fachsystematik

  • 409-04 Betriebs-, Kommunikations-, Datenbank- und verteilte Systeme

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