Abstract
This paper presents a generic hardware design which allows the composition of application specific datapaths at runtime. The architectural template consists of a grid of identical tiles which are connected by a lightweight network-onchip. A processor core is used to configure pre-synthesized basic processing elements to arbitrary tiles at runtime. The sum of these personalized processing elements forms an application specific datapath. The architectural template is well suited for application domains in which data are processed in form of streams and circumvents the problem of online-synthesis for applicationspecific datapaths which cannot be determined at design time. Furthermore, the template supports processing of several tasks and data streams in parallel. By means of an application example in the area of relational databases the usefulness of the proposed architecture is demonstrated.
| Originalsprache | Englisch |
|---|---|
| Titel | 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig) |
| Seitenumfang | 6 |
| Herausgeber (Verlag) | IEEE |
| Erscheinungsdatum | 01.12.2015 |
| Seiten | 1-6 |
| Aufsatznummer | 7393300 |
| ISBN (Print) | 978-1-4673-9406-2 |
| ISBN (elektronisch) | 978-1-4673-9405-5 |
| DOIs | |
| Publikationsstatus | Veröffentlicht - 01.12.2015 |
| Veranstaltung | International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015 - Riviera Maya, Mexico Dauer: 07.12.2015 → 09.12.2015 Konferenznummer: 119205 |
Strategische Forschungsbereiche und Zentren
- Querschnittsbereich: Intelligente Systeme
- Zentren: Zentrum für Künstliche Intelligenz Lübeck (ZKIL)
DFG-Fachsystematik
- 4.43-03 Sicherheit und Verlässlichkeit, Betriebs-, Kommunikations- und verteilte Systeme
UN SDGs
Dieser Output leistet einen Beitrag zu folgendem(n) Ziel(en) für nachhaltige Entwicklung
