A Dynamically Reconfigurable Packet-Switched Network-on-Chip

Thilo Pionteck; Carsten Albrecht; Roman Koch

doi:10.1109/DATE.2006.244035

A Dynamically Reconfigurable Packet-Switched Network-on-Chip

Thilo Pionteck, Carsten Albrecht, Roman Koch

Institut für Technische Informatik

Abstract

This paper presents the design of an adaptable NoC for FPGA based dynamically reconfigurable SoCs. At runtime, switches can be added or removed from the network, allowing to adapt the NoC to the number, size and location of currently configured hardware modules. By using dynamic routing tables, reconfiguration can be done without stopping or stalling the NoC. The proposed architecture avoids the limitations of bus-based interconnection schemes which are often applied in partially dynamically reconfigurable FPGA designs.

Originalsprache	Englisch
Titel	Proceedings of the Design Automation & Test in Europe Conference
Herausgeber (Verlag)	IEEE
Erscheinungsdatum	01.12.2006
Aufsatznummer	1656864
ISBN (Print)	3-9810801-1-4
DOIs	https://doi.org/10.1109/DATE.2006.244035
Publikationsstatus	Veröffentlicht - 01.12.2006
Veranstaltung	Design, Automation and Test in Europe - Munich , Deutschland Dauer: 06.03.2006 → 10.03.2006 Konferenznummer: 69442

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AB - This paper presents the design of an adaptable NoC for FPGA based dynamically reconfigurable SoCs. At runtime, switches can be added or removed from the network, allowing to adapt the NoC to the number, size and location of currently configured hardware modules. By using dynamic routing tables, reconfiguration can be done without stopping or stalling the NoC. The proposed architecture avoids the limitations of bus-based interconnection schemes which are often applied in partially dynamically reconfigurable FPGA designs.

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A Dynamically Reconfigurable Packet-Switched Network-on-Chip

Abstract

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